Figure 2. Intel Cyclone 10 GX Devices with 12 Transceiver Channels and One PCIe Hard
IP Block
Transceiver
Bank
GXBL1D
Transceiver
Bank
GXBL1C
Transceiver
Bank
Transceiver
Bank
CH5
CH4
CH3
CH2
CH1
CH0
Transceiver
Bank
Legend:
PCIe Gen1 - Gen2 Hard IP blocks with Configuration via Protocol (CvP) capabilities.
Cyclone 10 GX device with 12 transceiver channels and one PCIe Hard IP block.
PCIe
Gen1 - Gen2
Hard IP
(with CvP)
Figure 3. Intel Cyclone 10 GX Devices with 10 Transceiver Channels and One PCIe Hard
IP Block
Transceiver
Bank
GXBL1D
Transceiver
Bank
GXBL1C
Transceiver
Bank
Transceiver
Bank
CH5
CH4
CH3
CH2
CH1
CH0
Transceiver
Bank
Legend:
PCIe Gen1 - Gen2 Hard IP blocks with Configuration via Protocol (CvP) capabilities.
Cyclone 10 GX device with 10 transceiver channels and one PCIe Hard IP block.
PCIe
Gen1 - Gen2
Hard IP
(with CvP)
Figure 4. Intel Cyclone 10 GX Devices with 6 Transceiver Channels and One PCIe Hard
IP Block
Transceiver
Bank
GXBL1C Transceiver
Bank
CH5
CH4
CH3
CH2
CH1
CH0
Transceiver
Bank
GXBL1C
Note:
Legend:
PCIe Gen1 - Gen2 Hard IP block with Configuration via Protocol (CvP) capabilities.
Cyclone 10 GX device with six transceiver channels and one PCIe Hard IP block.
PCIe
Gen1 - Gen2
Hard IP (with CvP)
(1)
(1) Only CH5 and CH4 support PCIe Hard IP block with CvP capabilities.
1. Intel
®
Cyclone
®
10 GX Transceiver PHY Overview
UG-20070 | 2018.09.24
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Intel
®
Cyclone
®
10 GX Transceiver PHY User Guide
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