Microchip Technology Microsemi UG0677

Pma14
- Receiver14
- Figure 2 Transceiver Receiver15
- Figure 3 Receiver Input Buffer15
- Figure 4 Input Signal Path16
- Figure 5 CDR Lock Mode Options18
- Table 2 CDR Lock Mode Values18
- Table 3 Mode of Operations20
- Transmitter21
- Figure 6 Transceiver Transmitter21
- Figure 7 Transmit Output Driver22
Enhanced Receiver Management23
Table 4 ERM Ports23
Figure 8 Enhanced Receiver Management in XCVR Configurator24
Figure 9 Calibration Options for Enhanced Receiver Management Operations25
Figure 10 Exposing RX_READY_CDR and RX_VAL_CDR Pins25
Figure 11 DFE Options26
Table 5 DFE Options26
Figure 12 First Lock Calibration Waveform27
Figure 13 Disruption of Serial Rx Data Stream27
Figure 14 Restart after Initialization28
Figure 15 On-Demand Calibration Waveform29
Transceiver PCS Interface Modes30
- 8B10B30
- Figure 16 8B10B Data Path32
- Table 6 System Registers Affecting 8B10B Data Path33
- Table 7 8B10B Port List34
- 64B66B/64B67B37
- Table 8 64B6Xb Transmit Data Path Blocks, Fabric to PMA Order37
- Figure 17 64B6Xb Data Path38
- Table 9 64B6Xb Receive Data Path Blocks, PMA to Fabric Order38
- Table 10 System Registers Affecting 64B6Xb Data Path39
- Figure 18 64B66B Receive Sequence for 32-Bit Interface40
- Figure 19 64B66B Receive Sequence for 64-Bit Interface40
- Figure 20 64B66B Transmit Sequence for 64-Bit Interface41
- Figure 21 64B66B Transmit Sequence for 32-Bit Interface41
- Figure 22 64B67B Transmit Sequence for 32-Bit Interface42
- Figure 23 64B67B Receive Sequence for 32-Bit Interface43
- Table 11 64B66B/64B67B Port List43
- Pipe45
- Table 12 PIPE Port List46
- PIPE Interface Compliance Exceptions50
- Figure 24 Initial Receiver Detection Response for Receiver-Not-Present50
- PMA Only51
- Figure 25 Initial Receiver Detection for Receiver-Present51
- Figure 26 Subsequent Receiver Detection Where Prior Status was Receiver-Not-Present51
- Figure 27 PMA-Bus Waveform52
- Figure 28 PMA Only Data Path - 80-Bits52
- Figure 29 PMA Only Data Path - Less than or Equal to 40-Bits53
- Table 13 PMA Port List53
PCS/FPGA Fabric Interface55
- Non-Deterministic Interface56
- Figure 30 Global-Shared Clocking Example56
- Figure 31 Non-Deterministic Interface with FWF57
- Figure 32 Non-Deterministic Interface Transmit Timing Waveform57
- Figure 33 Non-Deterministic Transceiver Receive Timing Waveform57
- Deterministic Interface58
- Figure 34 Deterministic Timing Interface58
- Figure 35 Deterministic Transceiver Transmit Timing Waveform58
- Transceiver Clock Regions59
- Figure 36 Deterministic Transceiver Receive Timing Waveform59
- Figure 37 Transceiver Clock Regions59
- Transceiver Data Path Latency60
- Table 14 Clock Region Connectivity60
- Table 15 Transceiver Data Path Latency60
- Transceiver Clocking Use Cases61
- Table 16 Transceiver Interface Clocking Use Cases61
Transceiver Clocking62
- Transmit PLL62
- Figure 38 Transmit PLL62
- Table 17 Transmit PLL63
- Spread Spectrum Clocking64
- Figure 39 Spread Spectrum Clocking Modulation Mode64
- Transmit Lane Alignment65
- Figure 40 Using TXPLL_SSC for Upto Four Lanes65
- Figure 41 Using Txplls for Upto Four Lanes66
- Figure 42 FPGA Logic for TX Alignment (5 to 8 Lanes)67
- Transceiver Clocks68
- Figure 43 Reference Clock (REFCLK) Interface to Transmit PLL69
- Table 18 Transmit PLL Pin List69
- Figure 44 Typical Jitter Attenuator Application Scheme70
- Figure 45 Jitter Attenuation TXPLL71
- Table 19 Jitter Attenuation PLL Presets71
- Figure 46 JAPLL Custom Protocol Setting72
- Figure 47 Reference Clock Source Options72
- Figure 48 Rx JA Clock Frequency (XCVR Configurator)72
- Figure 49 Dedicated Transceiver Reference Clock Inputs73
- Table 20 XCVR REFCLK Defaults74
- Table 21 Reference Clock Input Buffer Standards75
- Figure 50 REFCLK Input Pin Diagram76
- Table 22 Polarfire Transceiver Resources76
- Figure 51 MPF100 Transceiver and Transmit PLL Layout77
- Figure 52 MPF200 and MPF300 Transceiver and Transmit PLL Layout78
- Figure 53 MPF500 Transceiver and Transmit PLL Layout79
PMA and PCS Resets80
Figure 54 PMA_ARST_N Block Diagram80
PCS Rate Switch between 8B10B and 64B66B Mode for CPRI82
Figure 55 PCS Rate Switch between 8B10B and 64B66B Mode82
Table 23 Port Crossover between the 8B10B and 64B66B Modes82
Table 24 System Registers Affecting 8B10B and 64B6Xb Data Paths85

4 Implementation88

5 Signal Integrity Conditioning115

Figure 90 Signal Integrity Conditioning Flow115

6 Simulation128

7 Debug and Testing129

8 Board Design Recommendations132

Brand	Microchip Technology
Model	Microsemi UG0677
Category	Transceiver
Language	English

Microchip Technology Microsemi UG0677 - User Manual

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Microchip Technology Microsemi UG0677 Specifications