Microchip Technology Microsemi UG0677 - Table 31 Transceiver Interface PCS Settings

Implementation
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 93
RX Data rate 250 Mbps – 12700 Mbps 5000 Mbps 10312.5 Mbps (STD
maximum)
RX CDR lock mode Lock to reference, Lock to data,
Burst Mode Receiver
2
, lock to
data with 2x gain
3
Lock to data
RX CDR reference clock source Dedicated and fabric Dedicated
RX CDR reference clock
frequency
4
Based on transceiver data rate
RX JA Clock Frequency Calculated based on
configuration
1. Enter the transceiver data rate (lane rate), and the TX clock division factor in the XCVR UI. Based on these settings, the TX_PLL
base data rate is calculated. The TX_BIT_CLK frequency is half of the TX_PLL base data rate. The TX_PLL base data rate must
be entered under the desired output clock option of the PF_TX_PLL block. The PF_TX_PLL generates the BIT_CLK output
(connected to the TX_BIT_CLK_0/1 input of PF_XCVR).
2. When Burst Mode Receiver (BMR) is selected, LANE_X_CDR_LOCKMODE[1:0] port is exposed.
3. Default Gain, slower CDR lock time, lower jitter tolerance 2x Gain, faster CDR lock time, higher jitter.
4. This input frequency is given by the user to support the integer feedback divider of the receiver PLL. From the drop-down, enter
a CDR reference clock frequency (MHz) value equal to the reference clock used to the Receiver PLL. The computation derives
the feedback divider used to clock the receiver data path.
Table 31 • Transceiver Interface PCS Settings
PCS Settings Options Default Details
PCS-fabric interface width 8, 10, 16, 20, 32, 40, 64, and 80
1
40
FPGA interface frequency
2
Computed
PMA Mode Enable CDR Bit-slip port Enable
8b10b encoding/decoding None
64b6xb gear box 64b66b
64b67b
64b66b If 64b6xb mode is enabled,
then PCS-Fabric interface
width must be 32- or 64-bit.
64b66b gear box Enable disparity Disabled Enabled for 64b67b -
Optional for 64b66b gear
box.
Enable scrambler/de-scrambler Disabled
Enable BER monitor state
machine
Disabled
Enable 32 bits data width Disabled
64b67b gear box Enable BER monitor state
machine
Disabled Enable 32 bits data width
Enable Disparity Enabled Cannot be enabled for
64b66b
Enable Scrambler/de-scrambler Disabled
Enable 32 bits data width Disabled
Soft PIPE interface PCIe Gen1 (2.5Gbps)
PCIe Gen2 (5.0Gbps)
PCIe Gen1 (2.5 Gbps)
1. Dependent on PCS settings.
Table 30 • Transceiver Interface PMA Settings
PMA Settings Options Default Details