Functional Description
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 27
The following table lists the port names and description for the 8b10b mode of PCS module.
pma_lane DES_CLK_CTRL DESMODE[2:0] Selects parallel bus width of
deserializer interface.
Must select the 40-bit
wide bus mode for 8b10b
functionality (3'd7).
SER_CLK_CTRL SERMODE[2:0] Selects parallel bus width of
serializer interface.
DES_CDR_CTRL3 SLIP_DES_CDR_SEL Selects source of CDR slip
control.
Must be 1'd0 so that the
fabric can control the
symbol alignment.
SLIP_DES_CDR_EN Optionally turns slip control off. Must be set to 1'd1.
Table 7 • 8b10b Port List
Port Name Direction Clock Description
LANE#_CDR_REF_CLK_#/LA
NE#_CDR_REF_CLK_FAB
Input Reference clock to lane CDR. Can be sourced from
either an FPGA clock or from a
XCVR_#[A,B,C]REFCLK_P/N pin.
LANE#_CLK_REF Input This port is exposed to user with Half-Duplex option.
LANE#_REF_CLK must be connected by the user to a
stable clock with same clock frequency as Recovered
clock such as the local clock.
LANE#_TX_PLL_REF_CLK_# Input Input clock from TX_PLL REF_CLK_TO_LANE output
pin. Included in CLKS_FROM_TXPLL_# BIF (bus
interface).
LANE#_TX_BIT_CLK_0 Input Clock from BIT_CLK of the XCVR TxPLL. Included in
CLKS_FROM_TXPLL_# BIF (bus interface).
LANE#_TX_PLL_LOCK_# Input Input lock status from TX_PLL LOCK output pin.
Included in CLKS_FROM_TXPLL_# BIF (bus interface).
LANE#_TX_DISPFNC[N:0]
1
Input TX_CLK_[R:G] The TX_DISPFNC is a 2-bit encoded setting per octet
where bit[1:0] is the lowest octet. The TX_DISPFNC
port size is 4-bit, 8-bit, or 16-bit respective to 16-bit, 32-
bit, or 64-bit PCS-Fabric interface widths.
The TX_DISPFNC encoding is as follows for each octet
per IEEE specification Clause 36 (802.3).
The octet swap feature is designed such that the fabric
marks the swap indicator on any octet of the interface. It
is not necessary to align the K28.5 to octet 0 or octet 2.
None - 2'b00 - Normally encode the octet with the
encoder's current running disparity.
Swap - 2'b01 - Search for tx_dispfnc = 1, swap next
octet when running disparity prior to ordered set is ‘+’.
ForcePlus - 2'b11 - Replace running disparity from
encoder with ‘+’ when encoding associated octet. This
tx_dispfnc occurs on any octet.
ForceMinus - 2'b10 - Replace running disparity from
encoder with ‘–’ when encoding associated octet. This
tx_dispfnc occurs on any octet.
LANE#_8B10B_TX_K[N:0]
2
Input TX_CLK_[R:G] Active-high signal indicating that TX_DATA contains
k-character information. This indicates that the input is a
k-character byte, not a data byte.
Table 6 • System Registers Affecting 8b10b Data Path
Register
Page xls Register Name Field Name Description Required Value
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