Microchip Technology Microsemi UG0677 - Figure 53 MPF500 Transceiver and Transmit PLL Layout

Functional Description
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 72
Figure 53 • MPF500 Transceiver and Transmit PLL Layout
PCIE1
PCIE0
Q0_TXPLL_SSC
Q0_TXPLL0
Q0_TXPLL1
Q1_TXPLL_SSC
Q1_TXPLL1
Q1_TXPLL0
Q3_TXPLL_SSC
Q3_TXPLL
Q1_LANE3
Q1_LANE2
Q1_LANE1
Q1_LANE0
Q3_LANE3
Q3_LANE2
Q3_LANE1
Q3_LANE0
Q0_LANE1
Q0_LANE2
Q0_LANE3
Q0_LANE0
Q2_TXPLL_SSC
Q2_TXPLL1
Q2_TXPLL0
Q2_LANE3
Q2_LANE2
Q2_LANE1
Q2_LANE0
Q4_TXPLL
Q4_TXPLL_SSC
Q4_LANE3
Q4_LANE2
Q4_LANE1
Q4_LANE0
Q5_TXPLL_SSC
Q5_TXPLL
Q5_LANE3
Q5_LANE2
Q5_LANE1
Q5_LANE0