Microchip Technology Microsemi UG0677 - Transmit Lane Alignment; Figure 40 Using TXPLL_SSC for Upto Four Lanes

Functional Description
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 58
3.5.3 Transmit Lane Alignment
Applications like Serial RapidIO, XAUI, DisplayPort, Interlaken, and JESD204B need transmit alignment
across multiple lanes. Transmit lane alignment depends on the number of lanes, total skew, fabric clock
frequency relative to the line rate, and number of TX PLLs. The method of alignment involves launching
a reset from the shared PLL to each TX lane after the PLLs are locked.
The transceiver PMA block supports transmit lane alignment for upto four lanes using the following
quad-based reset methods:
• Q#_TxPLL_SSC PLLs and its four lanes (quad) as shown in Figure 40, page 58.
• Q#_TxPLL[1:0] and two lanes each from the adjacent quads as shown Figure 41, page 59.
The transmit clock for each transceiver lane can be driven by an external or a quad PLL. The reset for
the TX lanes is based on the PLL selected. This reset is connected within the transceiver block to travel
with the transmit clock. All of the TX lanes for a given TX clock are reset by asserting the signal TX PLL
CLKRESET. To ensure a proper reset, stop the TX clocks for four clock cycles. With this quad-based
reset method, very low skew is achieved.
Figure 40 • Using TXPLL_SSC For Upto Four Lanes
TX_Bit_CLK
TX_CLK_RESET
TXPLL1
TX_Bit_CLK
TX_CLK_RESET
TXPLL0
TX Lane
TX Lane
TX Lane
TX_Bit_CLK
TX_CLK_RESET
TXPLL_SSC
TX Lane
TX_CLK_RESET
TX_Bit_CLK
TX_CLK_RESET
TX_Bit_CLK
TX_CLK_RESET
TX_Bit_CLK
TX_CLK_RESET
TX_Bit_CLK
QUAD