Functional Description
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 67
3.5.4.3.2 Reference Voltage Input
In this mode, the input interface supports two single-ended modes:
• Local reference input: a reference voltage is connected to the XCVR_REFCLK_N input, which is
used for the clock connected to the XCVR_REFCLK_P input. The resulting reference clock is
available on the REFCLK0 output (REFCLK1 output is unavailable with local reference input mode).
• Global reference input: this mode allows for two separate reference clock sources, where the
XCVR_REFCLK_P input is compared with a global transceiver reference called XCVR_VREF and is
output on REFCLK0. The XCVR_REFCLK_N input is simultaneously compared to the same
XCVR_VREF reference signal, and the result is output on REFCLK1. In this scenario, each
XCVR_REFCLK_P and XCVR_REFCLK_N pins can accept a single-ended clock source. The
resulting clock signals are available on REFCLK0 and REFCLK1 outputs, respectively.
Internal voltage reference circuitry is included when a reference voltage input is used. No external
voltage is required to the reference voltage input (XCVR_VREF) pin, which is internally connected.
Note: There is one XCVR_VREF signal per device that can be sourced from an external pin or an internal
reference voltage circuit. An internally generated voltage reference (VREF) is default. A user can
optionally use an externally supplied VREF if desired.
3.5.4.3.3 Single-Ended CMOS Input
In addition, the XCVR_REFCLK_P/N pins can connect a single-ended CMOS clock signal to the
REFCLK0 and REFCLK1 inputs. This allows two independent reference clocks to be applied to a XCVR
REFCLK inputs. XCVR_VREF is not used for single-ended CMOS reference clock input signaling.
3.5.4.3.4 XCVR REFCLK Usage
Transceiver Reference clock input standards will default to the following configurations dependent on the
selection of LVCMOS, Voltage Reference, or Differential selection in the REFCLK configurator.
The default can be changed using PolarFire I/O PDC constraints (not available in IOEditor).
-io_std <iostd>
-ODT_VALUE <odt>
-RES_PULL <res_pull>
-SCHMITT_TRIGGER <schmitt>
-USE_EXTERNAL_VREF <true, false>
-POWER_SUPPLY <power Supply for all Ports>
-EXTERNAL_VREF <true/false>
Note:
• By default, the VDD_XCVR_CLK power supply is set to 2.5 V. If 3.3 V is used, add it to all ports in
the PDC. If a port is not specified in the PDC, it takes the default setting. All REFCLK ports need to
be specified in the PDC to specify their location else the flow stops.
• The new options are case sensitive, the values are not.
• To turn OFF the odt, set the ODT_VALUE to 0.
• SSTL18I, SSTL18II, SSTL25I and SSTL25II inputs optionally have a VREF pin to set.
• PDC option is called USE_EXTERNAL_VREF <true/false> where the default is false to use the
internal VREF pin
Table 20 • XCVR REFCLK Defaults
Reference Clock
Mode I/O Std Resistor Pull Schmitt Trigger ODT VDDI
LVCMOS LVCMOS25 None OFF 0 2.5
Voltage Reference SSTL25I None OFF 0 2.5
Differential LVDS25 None OFF 100 2.5
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