Microchip Technology Microsemi UG0677 - Physical Constraints; Table 34 Physical Constraint Instances for XCVR

Implementation
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 103
4.4.2 Physical Constraints
Transceiver designs require physical constraints. These constraints provide placement guidance for the
embedded transceiver blocks such as XCVR_REF_CLK, XCVR_TXPLL, and XCVR. Select the
placement of the RXD and TXD transceiver pins and reference clock input pins by adding location
constraints to the design PDC file. Placement fails if the XCVR lane TX and RX I/Os, XCVR_REF_CLK
I/Os and TX_PLL locations are not explicitly placed. The Libero I/O Editor assists with the creation of
physical constraints using a GUI, see Adding Physical Constraints Using Libero, page 104.
For physical constraining by the user, the instance name is mapped to top-level physical pins based on
PolarFire device and package pin-outs found in the physical pin assignment tables (PPAT). The user
provides the constraint to the PDC file as listed in the following table.
For XCVR Lanes:
set_io –port_name <port name> \-pin_Name <package pin name> \-DIRECTION INPUT
For XCVR REFCLK:
set_io -port_name <refclk port name> \
-pin_name <package pin>\
-DIRECTION INPUT \
-io_std: See UG0686: PolarFire FPGA User I/O User Guide for information about available IO
Standards.
-ODT VALUE: See UG0686: PolarFire FPGA User I/O User Guide for information about available
ODT values.
Table 34 • Physical Constraint Instances For XCVR
XCVR Instance
1
1. Q# = Transceiver Quad identifier (Q0, Q1, and so on.)
Corresponding Top-level Pins
2
2. Pin-mapping to top-level pins can be found in the PolarFire pin-assignment tables (PPAT) for each
device and package type. For more information about PPATs, see
https://www.microsemi.com/products/fpga-soc/fpga/polarfire-fpga#documentation.
Q#_LANE0 XCVR_Q#_RX0_P/N
XCVR_Q#_TX0_P/N
Q#_LANE1 XCVR_Q#_RX1_P/N
XCVR_Q#_TX1_P/N
Q#_LANE2 XCVR_Q#_RX2_P/N
XCVR_Q#_TX2_P/N
Q#_LANE3 XCVR_Q#_RX3_P/N
XCVR_Q#_TX3_P/N
Q#_TXPLL_SSC Dependent on design clocking requirements
(see Figure 52, page 71 and Figure 53, page 72)
Q#_TXPLL0 Dependent on design clocking requirements
(see Figure 52, page 71 and Figure 53, page 72)
Q#_TXPLL1
3
3. Only TXPLL_SSC and TXPLL0 is available for Quad4 and Quad5. Refer Figure 52, page 71.
The default differential REFCLK value is set to 100 (
-ODT_VALUE 100). To disable the ODT
value, set the value of the differential REFCLK to 0 (
-ODT_VALUE 0 in the PDC file.
Dependent on design clocking requirements
(see Figure 52, page 71 and Figure 53, page 72)
Q#_REFCLK_A XCVR_Q#A_REFCLK_P/N
Q#_REFCLK_B XCVR_Q#B_REFCLK_P/N
Q#_REFCLK_C XCVR_Q#C_REFCLK_P/N