Functional Description
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 30
3.3.2 64b66b/64b67b
The 64b66b/64b67b (64b6xb) interface modes are used mainly for 10 Gbps-based protocols, 10G base
interface over Ethernet (10GBASE-R/KR), common public radio interface (CPRI) rates of 9.830 Gbps,
and 40GBASE-R standards. The 64b/66b encoder is used to achieve DC balance and sufficient data
transitions for clock recovery. It encodes 64-bit XGMII data and 8-bit XGMII control into 10GBASE-R
66-bit control or data blocks in accordance with Clause 49 of the IEEE802.3-2008 specification.
The following features are supported in the 64b6xb:
• Fabric width is selectable. Four and eight byte widths are available.
• Gearbox functions are set for 67-bit or 66-bit block size. The gearbox functions can be bypassed.
• Optional scrambler and descrambler 64b66b data.
• Optional test pattern generate/compare mode.
• Optional PRBS generate/compare mode.
• Optional disparity generate/check (applies to 64b67b data).
• Receiver block lock state-machine controlling the hunt for synchronization header boundaries is
available in two forms.
• The IEEE 802.3 Clause 49 state-machine loses lock when 16 invalid headers are observed
within a contiguous set of 64 headers.
• The IEEE 802.3 Clause 82 state-machine loses lock when 65 invalid headers are observed
within a contiguous set of 1024 headers.
Both block lock state-machines require an initial set of 64 contiguous valid headers to gain block
lock. The Clause 82 state-machine is specified for use with 40 G and 100 G links. One of these
state-machines must be enabled in order for the receiver to locate and lock onto the block
boundaries.
• Optional receiver IEEE 802.3 bit error rate monitor function.
• Optional data path delay status monitors for transmit and receive.
Note: Forward Error Correction (FEC) option of IEEE 802.3 10GBASE-KR is not supported by the 64b6xb
PCS.
The encoder uses per-lane block interfaces with a fabric interface to receive and transmit encoded data
and a PMA interface to send parallel data to the transceiver. This mode also supports the Interlaken
protocol by providing 64b67b with optional embedded gearing logic.
3.3.2.1 64b6xb Data Path Interface
An 64b6xb lane data path has the following interfaces:
• Fabric interface – a data path interface with soft-logic
• Internal clocks and resets interface
• PMA interface
• Parallel transmit data to the serializer
• Parallel receive data from the de-serializer
• Tx and Rx Fly-wheel FIFO(FWF)
• 64b6xb Transmit Data Path Blocks, Fabric to PMA Order
• 64b6xb Receive Data Path Blocks, PMA to Fabric Order
• System registers interface – controlling modes and options
The following figure shows an overview of the 64b6xb data path within the 64b6xb lane. The diagram is
intended to show the relative data and clock paths from the serial to fabric interface and vice-versa.
The fabric TX_DATA and RX_DATA ports are allocated to pin functions as described in 64B6xB Port List
Table 11, page 36. In addition to the fabric data pins, there are additional signals described in 64B6xB
portlist (Table 11, page 36) on the fabric interface for 64B6xB mode.
Table 8 • 64b6xb Transmit Data Path Blocks, Fabric to PMA Order
Tx Block Purpose
8B_to_4B Optionally compresses transmit bus width from 64-bits to 32-bits.
Tx Scrambler Implements IEEE 802.3 Clause 49 data scrambling. Same scrambling also specified for
use in Interlaken.
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