Microchip Technology Microsemi UG0677 - Libero Generated Files; Design Constraints; Timing Constraints

Implementation
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 101
4.3 Libero Generated Files
Libero SoC software automatically generates the required files after stepping through the design entry
steps of the transceiver. The following files are created:
• Netlist file—the RTL netlist instantiates the transceiver macros and related RTL wrappers based on
protocol specific functions.
• <design name>.sdc file—Timing constraints file in the case of TXPLL and XCVR configurators.
• <module name>.v, _syn_comps.v, _pre_comps.v
• HDL source files for all Synthesis and Simulation tools.
• HDL source files for Synopsys SynplifyPro Synthesis tool.
• HDL source files for Mentor Precision Synthesis tool.
Note: The entire file list and their file paths are maintained in mainfest.txt at <Project
Directory>/component/work/<Component name>/*_manifest.txt files.
Note: XCVR and PCIESS initialization data is available in the generated netlists of the TXPLL, XCVR, and
PCIE blocks. This is used to configure the blocks specifically for users design customization. See
Transceiver Initialization, page 107.
4.4 Design Constraints
Design constraints are either requirements or properties in the design. Constraining ensures transceiver
designs meets their performance goals, embedded block locations, and pin assignment requirements.
The software supports timing, physical, and netlist optimization constraints for the transceivers. Design
constraints can be set by either using Microsemi’s interactive tools or by importing constraint files directly
into the design session.
4.4.1 Timing Constraints
Timing constraints for the designs are required to meet the performance goals of the transceiver
interface. Specify timing constraints directly in the SDC or by using the timing constraints editor. The
following timing constraints must be methodically introduced into the design. Libero assists by
automatically generating timing constraints related to transceiver clock usage.
A component-level SDC file is created for every XCVR instance, which is pulled into the SDC file created
for the entire Libero design project as shown in the following example.
CDR reference clock source
Dedicated
create_clock -period <T> [get_pins {LANE<n>/REF_CLK_P}]
Fabric
create_clock -period <T> [get_pins {LANE0<n>RX_REF_CLK}]
Interface clock
Global
create_clock -period <T> [get_pins {LANE<n>/TX_CLK_G}]
create_clock -period <T> [get_pins {LANE<n>/RX_CLK_G}]
Regional or Regional (Deterministic)
create_clock -period <T> [get_pins {LANE<n>/TX_CLK_R}]
create_clock -period <T> [get_pins {LANE<n>/RX_CLK_R}]
Global-shared Mode
create_clock -period <T> [get_pins {LANE<n>/TX_CLK_G}]
create_clock -period <T> [get_pins {LANE<n>/RX_CLK_G}]
create_clock -period <T> [get_pins {LANE<n>/TX_CLK_R}]