Microchip Technology Microsemi UG0677 - Table 24 System Registers Affecting 8 B10 B and 64 B6 Xb Data Paths

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Functional Description

Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 78

The following table outlines the affected registers that must be modified during rate switching.

Table 24 • System Registers Affecting 8B10B and 64B6xB Data Paths

Page xls Register Name Field Name Description

Required Value for

8B10B

Required Value for

64B6xB

pcslane L8_R0 L8_TXENCSW

APSEL

Selects between

1000BASE-X/T and

Fibre Channel octet-

swapping modes.

Optional:

0=1000BASE-X/T,

1=Fibre Channel

Don’t-care

L8_GEARMOD

E[1:0]

Sets data path width

of FWF interfaces.

Must be consistent

with clock selections

for txfwf_rclk and

rxfwf_wclk.

Don’t-care

LOVR_R0 FAB_IFC_MOD

E[3:0]

Selects path through

fabric and FWF

overlay blocks.

meanings of the

epcs_tx_data and

epcs_rx_data pins

based on the setting

of the pcslane

LOVR_R0:PCSPMA_

IFC_MODE[3:0]

control register field.

The

PCSPMA_IFC_MOD

E is one-hot encoded

as follows:

0b0100 == 8B10B

mode

PCSPMA_IFC_MO

DE is one-hot

encoded as follows

0b0010 == 64B6xB

mode

PCSPMA_IFC_

MODE[3:0]

Selects lane mode for

driving data into the

SerDes serializer.

LCLK_R0 LCLK_EPCS_R

X_CLK_SEL

[1:0]

Chooses which clock

is sent to fabric on

epcs_rx_clk port.

Usually this should be

set to 2’d1 so that the

frequency of the fabric

is the same as the

internal side of the

FWF. However

variations are

possible if the use of

the Rx FWF

synchronous enable

will be employed. See

FWF description for

further information.

2’d1

LCLK_EPCS_T