Microchip Technology Microsemi UG0677 - Figure 51 MPF100 Transceiver and Transmit PLL Layout

Functional Description
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 70
Figure 51, page 70, Figure 52, page 71, and Figure 53, page 72 shows the arrangement of the
transceiver quads, the connectivity of lanes, transmit PLLs, and embedded PCIe blocks for the MPF100,
MPF200, MPF300, and MPF500 device. This arrangement ensures package compatibility for all of the
devices in the PolarFire family. For example, if a package supports all of the devices of the PolarFire
family and a PCIe block is used on the smallest device, then the same PCIe block is available on the
same package pins for all other devices in the family.
Figure 51 • MPF100 Transceiver and Transmit PLL Layout
1. MPF200-FCG484 and FCVG484 packages only support up to eight XCVR lanes and six TXPLLs.
Q0_TXPLL_SSC
Q0_TXPLL1
Q0_TXPLL0
Q1_TXPLL_SSC
Q1_TXPLL1
Q1_TXPLL0
Q1_LANE0
Q1_LANE1
Q1_LANE2
Q1_LANE3
Q0_LANE2
Q0_LANE1
Q0_LANE0
Q0_LANE3
PCIE1
PCIE0