Microchip Technology Microsemi UG0677 - Deterministic Interface; Figure 34 Deterministic Timing Interface; Figure 35 Deterministic Transceiver Transmit Timing Waveform

Functional Description
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 51
3.4.2 Deterministic Interface
Low-latency regional clocks with a specific mode of the FWF are used when a zero-cycle path is
required; for example, by protocols such as CPRI and JESD204B that require both receive and transmit
paths have a fixed deterministic latency as expressed in number of clock cycles. In this case, data is
interfaced directly to capture registers while the clock is routed on regional clock resources. The regional
clock does not have the large clock insertion delay as the global clock network. A regional clock can
easily achieve timing closure to the fabric with this small amount of clock delay. Deterministic timing is
optionally selected in the Libero Transceiver configurator by choosing the deterministic regional options,
see Table 32, page 94.
Figure 34 • Deterministic Timing Interface
Figure 35 • Deterministic Transceiver Transmit Timing Waveform
Transmit
PMA
Regional or
Global Clocks
XCVR_TX
TXPLL
XCVR_REFCLK
TX_DATA
Receive
PMA
RX_DATA
Recovered Clock
REFCLK
XCVR_RX
TX_CLK_OUT
RX_CLK_OUT
Regional or
Global Clocks
Tx and Rx PCS to
FPGA Fabric Interface
TX_CLK
TX_CLK
(at fabric FF)
TXDATA
Valid
Note: TXCLK_FABRIC at PCS I/F after Regional clock route