Microchip Technology Microsemi UG0677 - Transceiver Data Path Latency; Table 14 Clock Region Connectivity; Table 15 Transceiver Data Path Latency

Functional Description
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 53
Users need to understand the regional clock implications when targeting designs that may migrate to
different device sizes. The user should also use this in pin planning of boards when desiring to drive I/O
from the transceiver clocks.
See UG0684: PolarFire FPGA Clocking Resources User Guide for more information about regional clock
resource regions.
3.4.4 Transceiver Data Path Latency
Transceiver data path latency is defined, when the earliest serial bit appears in bus bit 0 for both transmit
and receive interfaces of PMA mode. The PMA mode data path can be setup for different transmit and
receive widths as needed. Clock phase latency is not considered.
Note: 8b10b mode uses 20, 40, and 80 PmaPcsWidth. PIPE modes uses 40 PmaPcsWidth.
Table 14 • Clock Region Connectivity
Device Region FPGA Fabric Resource Count
IO 4LUT DFF MATH SRAM URAM CCC (PLL/DLL)
(CCC_NE, CCC_SE)
MPF100T One Only 120 49260 49260 152 160 456 4(PLL/DLL) (CCC_NE,
CCC_SE)
MPF200T Top 60 49980 49980 152 160 456 2- CCC (PLL/DLL)
(CCC_SE)
Bottom 60 37296 37296 114 120 342 2- CCC (PLL/DLL)
(CCC_SE)
MPF300T Top 96 80652 80652 248 256 744 2- CCC (PLL/DLL)
(CCC_NE)
Bottom 96 60192 60192 186 192 558 2- CCC (PLL/DLL)
(CCC_SE)
MPF500T Top 120 75468 75468 234 240 702 2- CCC (PLL/DLL)
(CCC_NE)
Middle 0 102516 102516 312 320 936 0
Bottom 120 75468 75468 234 240 702 2- CCC (PLL/DLL)
(CCC_SE)
Table 15 • Transceiver Data Path Latency
PCS
Mode PCS Fabric Width PMA PCS Width Transmit Latency (UI) Receive Latency (UI) Total Latency (UI)
PMA 8 8 82 58.5 140.5
PMA 10 10 100 73.4 173.4
PMA 16 16 148 122.4 270.4
PMA 20 20 184 153.6 337.6
PMA 32 32 292 250.5 542.5
PMA 40 40 364 313.5 677.5
PMA 64 32 452 410.5 862.5
PMA 80 40 564 513.5 1077.5
8b10b 40 40 404 314 718
8b10b 80 40 564 513.5 1077.5