Microchip Technology Microsemi UG0677 - Figure 61 PF_XCVR_REF_CLK with Differential Input and Single Output Clock; Figure 62 PF_XCVR_REF_CLK with Fabric Output Clock

Implementation
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 85
Figure 61 • PF_XCVR_REF_CLK With Differential Input and Single Output Clock
4. Optionally enable a connection to the FPGA fabric for either/both reference clock 0 or reference
clock 1. When enabled, a related port of the associated reference clock is exposed for fabric routing.
Figure 62 • PF_XCVR_REF_CLK With Fabric Output Clock
5. Click OK after making desired selections.
When the Reference Clock configurator generates the reference clock block, specify the desired IP
Standard. This is completed by adding the desired IO to the PDC file. For more information about adding
the IO to the PDC file, see Physical Constraints, page 103.
For more information about XCVR REFCLK input configuration, see XCVR REFCLK Usage, page 67.
The PF_XCVR_REF_CLK allows a global routing connection to the FAB_REF_CLK output via a CLKINT
global buffer. The FAB_REF_CLK output uses regular fabric routing resources and the connection
traverse half the device before connecting onto a CLKINT fabric Global Buffer at the center of the chip.
FAB_REF_CLK clock is potentially more susceptible to fabric switching noise, depending on the design,
which could lead to an unpredictable amount of clock jitter on that clock being broadcasted to the fabric.