Microchip Technology Microsemi UG0677 - Table 6 System Registers Affecting 8 B10 B Data Path

Functional Description
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 26
3.3.1.4 8b10b System Registers
There are specific registers used for configuring the 8b10b lane function options in the PolarFire Device
Register Map. Other fields are required to properly program the clocks, resets, XCVR, and lane overlay
blocks and data path steering. Required system register field setting combinations required for enabling
8b10 lane usage.
Table 6 • System Registers Affecting 8b10b Data Path
Register
Page xls Register Name Field Name Description Required Value
pcslane L8_R0 L8_TXENCSWAPSEL Selects between 1000BASE-
X/T and Fibre Channel octet-
swapping modes.
Optional: 0=1000BASE-
X/T, 1=Fibre Channel
L8_GEARMODE[1:0] Sets data path width of FWF
interfaces.
Must be consistent with
clock selections for
txfwf_rclk and rxfwf_wclk.
LOVR_R0 FAB_IFC_MODE[3:0] Selects path through fabric and
FWF overlay blocks.
Must be set to the 8b10b
value (3'd4).
PCSPMA_IFC_MODE[3:
0]
Selects lane mode for driving
data into the SerDes serializer.
LCLK_R0 LCLK_EPCS_RX_CLK_
SEL [1:0]
Chooses which clock is sent to
fabric on epcs_rx_clk port.
Usually this should be set
to 2'd1 so that the
frequency of the fabric is
the same as the internal
side of the FWF.
However variations are
possible if the use of the
Rx FWF synchronous
enable will be employed.
See FWF description for
further information.
pcslane LCLK_R0 LCLK_EPCS_TX_CLK_
SEL [1:0]
Chooses which clock is sent to
fabric on epcs_tx_clk port.
LCLK_PCS_RX_CLK_S
EL [1:0]
Defines clock module's source
for pcs_rx_clk.
Must be set to 2'd3 for all
applications using 8B10B
function.
LCLK_PCS_TX_CLK_S
EL [1:0]
Defines clock module's source
for pcs_rx_clk.
LCLK_RXFWF_WCLK_
SEL [1:0]
Defines clock module's source
for rxfwf_wclk.
Must be consistent with
L8_GEARMODE setting.
LCLK_TXFWF_RCLK_S
EL [1:0]
Defines clock module's source
for txfwf_rclk.
LCLK_RXFWF_WCLK_
PIPE
Defines whether Rx FWF is
clocked by Tx side clocks or
Rx side clocks.
Must be set to 1'd0 for
8B10B functionality.
LCLK_R1 LCLK_ENA_8B10B_RX_
CLK
Instructs clock module to drive
8B10B pcs_rx_clk.
Must be set to 1'd1 for
8B10B operation.
LCLK_ENA_8B10B_RX
FWF_WCLK
Instructs clock module to drive
8B10B rxfwf_wclk.
LCLK_ENA_8B10B_TX_
CLK
Instructs clock module to drive
8B10B pcs_tx_clk.
LCLK_ENA_8B10B_TXF
WF_WCLK
Instructs clock module to drive
8B10B txfwf_rclk.