Microchip Technology Microsemi UG0677 - Transceiver Clocking Use Cases; Table 16 Transceiver Interface Clocking Use Cases

Functional Description
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 54
3.4.5 Transceiver Clocking Use Cases
Each transceiver quad can source a global clock directly. Transceiver designs should use regional clocks
for the interface logic when possible. This reduces over use of global clocks. In many cases, transceiver
designs can share global clocks when multiple interfaces are used, depending on protocol requirements.
Only one global clock is supported per transceiver quad. See DS0141: PolarFire FPGA Datasheet for AC
performance information. For information about connectivity of the transceivers to the global clock
network, see UG0684: PolarFire FPGA Clocking Resources User Guide.
The following table lists the transceiver interface clocking use cases in the Libero SoC software, which
uses presets per protocol. See PCS/FPGA Fabric Interface, page 48 for explanation of system clock
source modes.
Table 16 • Transceiver Interface Clocking Use Cases
Preset Width Rx Tx
1
1. Shared implies that multiple lanes use common clock resources.
System Clock Source
1
10GBASE-R x1 Regional Global Global from XCVR Tx
10GBASE-R Multiple Regional Global shared Global from XCVR Tx shared
10GBASE-KR x1 and Multiple Regional Regional
SGMII/1000BASE x1 Regional Regional Global from XCVR Tx
SGMII/1000BASE Multiple Regional Global shared Global from XCVR Tx shared
JESD204B x1 Regional Global Global from XCVR Tx shared
JESD204B xN Regional Global shared Global from XCVR Tx shared
CPRI x1 Regional Regional Global
CPRI xN Regional Regional Global shared
Interlaken xN Regional ≥ Global
2
2. Uses regional clock and moves to global clock resources in the FPGA fabric.
Global shared Global from XCVR Tx shared
XAUI x4 Regional Global shared Global from XCVR Tx shared
RXAUI x2 Regional Global shared Global from XCVR Tx shared
SDI
3
x1 Global Global Global
SDI
3
Multiple Global Global shared Global
LiteFast
3
x1 Global Global Global from XCVR Tx and Rx
LiteFast
3
xN Regional ≥ Global
2
Global shared Global from XCVR Tx (shared) and
Rx
LiteFast
3
x1 and Multiple Global Global shared Global from XCVR Tx (shared) and
Rx (per interface)
QSGMII x1 Regional Regional Global 125 MHz
QSGMII Multiple Regional Global shared Global 125 MHz Shared
SATA
3
x1 Global Tx Global Tx Global Tx
SATA
3
Multiple Global Tx Global Tx Global Tx (not shared)
SRIO x1 Regional Global Global
SRIO xN Regional Global shared Global
SRIO Multiple Regional Global (per
interface)
Global
Fiber Channel x1 Regional Global Tx Global Tx
Fiber Channel Multiple Regional Global Tx shared Global Tx Shared