Signal Integrity Conditioning
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 110
5.2 Receiver
The receiver deserializes high-speed serial data received through the input buffer by creating a parallel
data stream for the FPGA fabric and recovering the clock information from the received data. For more
information about receiver, see Receiver, page 7.
5.2.1 Rx Insertion Loss
Receiver insertion loss is used to match the PCB qualities of the system. The predefined settings are
used to statically adjust the receiver CDR and DFE. The CDR and DFE parameters are assigned based
on a targeted data rate and backplane model. CDR uses only the CTLE capabilities of the PMA receiver.
The DFE uses combination of CTLE with DFE optimizations. To start the transceiver design, select the
Rx Insertion loss values in Libero. Libero adjusts to the best known setting based on the data rate. If the
pre-defined settings do not achieve the best performance, users can fine-tune the Rx CTLE settings to
precisely match their system requirements after initial system bring-up.
Backplane or PCB Length, that is, Reach definitions are based upon number of connectors and overall
insertion loss as per the CEI-11G SR, MR and LR specifications defined by Tyco Electronics Z-Pack
Tinman testing platform. See Transceivers Insertion Loss, page 129.
See AC483: PolarFire FPGA Transceiver Signal Integrity Application Note for information about the data
rate range and models of backplane length.
5.2.2 Rx CTLE
CTLE at the receiver end is a typical equalization technique for equalizing the incoming signal to a flat
response. CTLE is used to reduce the low-frequency component of the signal while boosting the high-
frequency component. The receiver equalization settings are a function of the cut-off frequency and the
amplitude gain across data rates. The equalizer circuitry can be tuned to compensate for the signal
distortion due to the high frequency reduction of the physical channel of the PCB and interconnect.
For example, an under-equalized channel cannot adequately open the eye, whereas over-equalization
can produce a channel with high jitter.
Correct equalization has optimal eye opening with low noise and low jitter. Rx insertion loss default
settings sets the CTLE. AC483: PolarFire FPGA Transceiver Signal Integrity Application Note lists the
combination of settings that help the user to find the best response to the incoming signal based on data
rate “buckets”. Within each bucket, there are optimized settings based on gain and peaking. When using
DFE designs, users should not alter the predefined values of CTLE. These values are optimized to work
in conjunction with the DFE configuration based on Rx insertion defaults as listed in following table.
5.2.3 Rx Termination
Within the Rx buffer, a calibrated input termination can be set having three—85 or 100 or 150 —
available differential impedances. The input impedance can be configured to match the system
requirements.
5.2.4 AC/DC Coupled Connection
DC coupled connection option is set for using AC or DC coupled channels to the receiver. The PolarFire
does include an internal coupling capacitor option, however, it also includes internal biasing circuitry
required for AC coupled applications.
• AC coupled with external cap. Vcim is internally generated.
• DC coupled – Link partner is in control of the Vcim through the incoming signal.
Note: For AC coupled with external cap, user must still place ac-coupling capacitor on PCB for AC coupled
connection.
AC-coupling or DC-coupling is configured through the PolarFire XCVR Signal Integrity options, which is
available in Libero SoC v12.2 and later. Coupling options can be set in the Signal Integrity View tab
(open the I/O Editor > XCVR View).
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