Microchip Technology Microsemi UG0677 - PIPE Interface Compliance Exceptions; Figure 24 Initial Receiver Detection Response for Receiver-Not-Present

Functional Description
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 43
Note: LANE# can be 0, 1, 2, and 3. [R:G] naming is generated based on the use of regional or global resources
that are selected with Libero.
3.3.4 PIPE Interface Compliance Exceptions
The PIPE Interface complies with Intel's Specification version 4.0 with the following exceptions.
• P1 to P0 power-state, PhyStatus pulse response is approximately 30 microseconds delayed from
the request to enter P0. The long delay is caused by waiting for the Rx PLL to spin-up and stabilize.
The P0-entry is observed externally as a long delay before sending training patterns. The training
pattern delay is a fatal protocol error.
• PCI-Express receiver detection has the following issues when used with soft PIPE interface.
• A receiver detection returning a Receiver-Not-Present status does so with an oscillating
PhyStatus pulse train. MAC-side LTSSM logic must ignore all but the first PhyStatus pulse of the
oscillation.
• A subsequent receiver detection operation N, begins a receiver detect, but immediately returns
the status of detection N-1 via PhyStatus and RxStatus when N > 0. The very first receiver
detection (N = 0) waits until the conclusion of the receiver detect activity and returns its status
via PhyStatus and RxStatus.
The following figure shows how PIPE interface signals behave when the first detection finds no
connected receiver. The response time in simulation is fixed for a given reference clock frequency due to
the means of modeling the XCVR. The XCVR model has a fixed reflection time of the common-mode
voltage step. In real silicon, the reflection time depends upon the termination network, and this also
determines when PIPE PhyStatus pulse occurs.
Figure 24 • Initial Receiver Detection Response For Receiver-Not-Present
1. In the MPF500 devices, the TX_CLK_R and RX_CLK_R pins of XCVR lanes placed in the PCIESS(Q0) and GPSS1(Q1) quads
cannot drive I/Os.
PCLK
TxDetectRx
P1 (2'b01)
PowerDown
PhyStatus
RxStatus
3'b000
Oscillation persists
through start of next
detection.
This is a no-connect
response.
Simulation: Approximately 3.4 μs
Reality: 0.4 to 1 μs