Functional Description
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 42
LANE#_RX_BYPASS_DATA Output Async RX_BYPASS_DATA output is a low-speed bypass of the
differential receiver that is used for the receive pads.
This is a a low-frequency out-of-band debug signal.
LANE#_PHYSTATUS Output RX_CLK_[R:G] Signals that the PHY has completed its setup and is
ready for data traffic. It is also used to indicate
successful transition from power management state, rate
change, and receive detection.
LANE#_RX_VAL Output RX_CLK_[R:G] LANE#_RX_VAL indicates that the XCVR data path is
initialized. The parallel bus of LANE#_RX_DATA[N:0]
contains actual data recovered from the serial stream
when LANE#_RX_VAL = 1.
In PIPIE mode, the Rx PCS logic self-resets when the
CDR is not locked. In this mode, LANE#_RX_VAL rises
just after LANE#_RX_READY rises. If you want to
control Rx PCS reset, hold Rx PCS in reset when
LANE#_RX_READY is low and release, when
LANE#_RX_READY goes high. Once Rx PCS is
released from reset, LANE#_RX_VAL rises to indicate
the Rx parallel data is valid.
In PIPE mode, the LANE#_RX_VAL is qualified when the
CDR locks and the initial comma/word alignment occurs.
LANE#_RX_READY Output Rises when the CDR is phase-locked to the incoming
data transitions and the de-serializer is powered-up. If
there is no incoming data to the CDR then the
RX_READY is low. The primary purpose of this pin is
communicating to fabric that the CDR is locked to serial
input data and is producing valid clocking.
Note: In a loopback case while looping the local
transmitter output to the receiver input, it is necessary to
take the Tx out of reset to ensure valid serial transitions,
allowing the Rx CDR to lock. The system deadlocks, if
the user waits till Rx CDR locks before the Tx is released
from reset.
LANE#_RX_IDLE Output Receive electrical-idle detection flag. Asserts
asynchronously, but de-asserts synchronously to the
RX_CLK_OUT rising edge.
LANE#_TX_CLK_STABLE Output Transmit transceiver/PCS lane ready flag. This flag is 1
when the transmit PLL is locked to the reference clock.
LANE#_TX_CLK_[R:G]
1
Output Global or regional transmit clock to fabric.
PIPE_CLOCK Output In PCIe Gen1/Gen2 modes of Soft PIPE PCS setting,
there is only one TX_CLK_[R:G] for all the 4 lanes that
could be configured in single XCVR configurator
instance, that is, LANE0_TX_CLK_[R:G] (renamed as
PIPE_CLOCK). This PIPE_CLOCK is commonly used
for all the lanes. Internally, both RX_FWF_CLK and
TX_FWF_CLK (internal ports on the XCVR macro) of
each lane are connected to the PIPE_CLOCK
(LANE0_TX_CLK_R/G) through RCLKINT/CLKINT.
LANE#_TXD_N Output Transceiver transmitter differential output.
LANE#_TXD_P Output Transceiver transmitter differential output.
Table 12 • PIPE Port List (continued)
Port Name Direction Clock Description
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