Functional Description
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 41
LANE#_TXELECIDLE Input TX_CLK_[R:G] When this signal is asserted high, it forces the
transmitter to the electrical idle state regardless of power
states. When this signal is de-asserted, valid data from
TXDATA and TXDATAK are transmitted in the P0 state. If
the PHY is in the P2 state, a beacon must be transmitted
when TXELECIDLE is de-asserted. In the P0s and P1
states, TXELECIDLE must be asserted. The use of this
signal is also affected by the PHY power state since
there are some states in which the transmitter must be
electrically idle. See the PHY Interface for the PCI
Express for more detail.
LANE#_PCS_ARST_N Input Asynchronous active-low reset for PCS lane.
LANE#_PMA_ARST_N Input Asynchronous active-low reset for PMA lane.
LANE#_RXD_N Input Transceiver receiver differential input.
LANE#_RXD_P Input Transceiver receiver differential input.
LANE#_RXELECIDLE Output RX_CLK_[R:G] The PCIe receiver pins detect an electrical idle state on
the link. High indicates receiver detection of electrical
idle, and low indicates beacon signaling when in P2.
LANE#_RXSTANDBYSTATUS Output RX_CLK_[R:G] The PHY uses this signal to indicate its Rx Standby
state.
0: Active
1: Standby
LANE#_RX_DATA[39:0] Output RX_CLK_[R:G] Parallel data bus from the PCS to the fabric. The
PF_XCVR send/receive order is low to high byte.
When the soft PCIe IP design is used, then RXDATA is
40 bits wide; otherwise, it is 32 bits wide (the upper byte
is ignored).
LANE#_RXDATAK[3:0] Output RX_CLK_[R:G] The data#/control indicator(s) for the received symbols
on the RXDATA bus:
0: RXDATA contains data
1: RXDATA contains ordered sets
If the soft PCIe IP is used, then RXDATAK is ignored.
LANE#_RXVALID Output RX_CLK_[R:G] Qualifies the data on RXDATA and RXDATAK. When this
signal is asserted, the data on the receive data bus is
valid, and the PHY has achieved symbol lock.
LANE#_RXSTATUS[2:0] Output RX_CLK_[R:G] Delivers receiver status and error codes for the received
data and receiver detect status from the PHY to the
MAC; for example, SKP symbol added or removed,
disparity error, elastic buffer overflow or underflow,
8b10b decode error, and so on.
0 0 0: Received data OK
0 0 1 1: SKP added
0 1 0 1: SKP removed
0 1 1: Receiver detected
1 0 0: Code error
1 0 1: Elastic buffer overflow
1 1 0: Elastic buffer underflow
1 1 1: Receive disparity error
Table 12 • PIPE Port List (continued)
Port Name Direction Clock Description
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