Functional Description
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 40
POWERDOWN[1:0] Input TX_CLK_[R:G] These inputs place the transceiver into one of four power
states:
P0: normal operational mode.
P0s: PCLK remains on, but the receiver conserves
power; entered when the receiver detects electrical idle.
Corresponds to link state L0s.
P1: PCLK remains on; both the receiver and transmitter
are in electrical idle. Corresponds to link state L1.
P2: PCLK is off. The PHY must minimize power
consumption as it must operate within the V
AUX
limits.
Corresponds to link state L2.
See the PHY Interface for the PCI Express for more
details on PHY power management.
PCIE_RATE[1:0] Input TX_CLK_[R:G] Controls the link signaling rate.
In PCIe mode:
00: Gen1 (2.5 Gbps)
01: Gen2 (5.0 Gbps)
TXMARGIN[2:0] Input TX_CLK_[R:G] Selects transmitter voltage levels:
000: TxMargin value 0. Normal operating range
001: TxMargin value 1. 800 mV–1200 mV for full swing
or 400 mV –700 mV for half swing
010: TxMargin value 2 (required). Vendor defined
011: TxMargin value 3 (required). Vendor defined
100: TxMargin value 4 (required). 200 mV–400 mV for
full-swing or 100 mV–200 mV for half-swing
101: TxMargin value 5 (optional). 200 mV–400 mV for
full-swing or 100 mV–200 mV for half-swing
110: TxMargin value 6 (optional). 200 mV–400 mV for
full swing or 100 mV–200 mV for half-swing
111: TxMargin value 7 (optional). 200 mV–400 mV for full
swing or 100 mV–200 mV for half-swing
TXDEEMPH Input TX_CLK_[R:G] Selects transmitter de-emphasis:
0: 6 dB de-emphasis at 5 Gbps
1: 3.5 dB de-emphasis at 5 Gbps
PIPE implementations that only support 2.5 Gbps
signaling rate do not implement this signal.
TXSWING Input TX_CLK_[R:G] Controls transmitter voltage swing:
0: Full swing
1: Half swing
LANE#_RXPOLARITY Input TX_CLK_[R:G] This active-high signal indicates the PHY to do a polarity
inversion on the received data.
LANE#_RXSTANDBY Input TX_CLK_[R:G] Used to set the RxStandby state:
0: Active
1: Standby
Table 12 • PIPE Port List (continued)
Port Name Direction Clock Description
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