Revision History
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 2
• Information about new latency was updated. See Table 15, page 53.
• Information about Transceiver Data Path Latency, page 53 was added.
• Information about footnote was updated. See Table 21, page 68.
• Information about PCS Rate Switch Between 8b10b and 64b66b Mode for CPRI, page 75 was
added.
• Information about MPF500 Transceiver and Transmit PLL Layout was updated. See Figure 53,
page 72.
• Information about JA PLL settings for each preset was added. See Jitter Attenuator, page 63.
• Information about Transceiver Modes, page 99 was added.
• Information about PMA and PCS Resets, page 73 was updated.
• Information about Custom Protocol Settings, page 65 was added.
• Information about Table 7, page 27, Table 11, page 36, Table 12, page 39, and Table 13, page 46
was updated.
1.5 Revision 5.0
The following is a summary of the changes in this revision.
• Information about SATA sub-mode was removed from PIPE, page 38.
• Information about RX_IDLE was updated. See Table 7, page 27, Table 11, page 36, and Table 13,
page 46.
• Information about LANE#_TX_WCLK input pin was added. See PCS/FPGA Fabric Interface,
page 48.
• Information about Transceiver Clock Regions, page 52 was added.
• Information about Reference Clock Disruptions, page 69 was added.
• Information about Jitter Attenuator, page 63 was added.
• Information about REFCLK input pins were updated. See Reference Clock Input Pins, page 68.
• Information about PMA and PCS Resets, page 73 was added.
• Information about the interface clocks for the Transceiver PLL was updated. See Table 32, page 94.
• Information about Enhanced Receiver Management, page 16 was added.
• Information about PIPE Interface Compliance Exceptions, page 43 was added.
1.6 Revision 4.0
The following is a summary of the changes in this revision.
• Updated the document for Libero
®
SoC PolarFire v2.3 release.
• Added information about burst mode receiver, see CDR Options, page 10.
• Added information about the alignment of transmit lanes, see Transmit Lane Alignment, page 58.
• Added information about Tx loss insertion, see Tx Insertion Loss, page 109.
• Added a footnote under Table 34, page 103 that describes how to disable the ODT value for the
differential REFCLK.
• Added a footnote under Table 32, page 94 that describes the minimum pulse width for the PMA
reset signal.
1.7 Revision 3.0
The following is a summary of the changes in this revision.
• Information about 8b10b, 64b66b, and PMA only features was added. See 8b10b, page 23,
64b66b/64b67b, page 30, and PMA Only, page 44.
• Information about signal integrity was added. See Signal Integrity Conditioning, page 108.
• Information about Bit-slip was updated. See Bit Slip, page 11. 8b10b does not support bit slip
mechanism.
1.8 Revision 2.0
The following is a summary of the changes in this revision.
• Information about 8b10b, 64b66b, and PMA only features was added. See 8b10b, page 23,
64b66b/64b67b, page 30, and PMA Only, page 44.
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