Functional Description
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 10
3.1.1.5 Eye Monitor
The eye monitor is on-device circuitry to visualize the post-equalization signal quality in the receive path
while the data path is still active in the system. The non-destructive eye monitor runs a separate sampler
in parallel with the CDR and DFE data sampler. This permits the system to remain operational while the
eye monitor is functioning.
The eye monitor systematically adjusts the offsets across the complete eye, calculates the bit-error rate
(BER) for each offset setting, then correlates the BER and offset to statistically rebuild the eye diagram.
Eye diagram statistics can be read and reconstructed using the Libero SmartDebug tools, which permits
access through a JTAG interface for transceiver debugging and test access.
Swing and de-emphasis can be configured in hundreds of combinations. It is, however, very
cumbersome for the user to tune these when optimizing the transceiver input. The eye monitor feature
eases the need to go through the manual steps to find the adjustments. It is used as part of the
CTLE/DFE auto-calibration. The eye monitor feedback mechanism optimizes the correct DFE settings by
using a duplicate DFE circuit to monitor and adjust the incoming data stream.
3.1.1.6 Receive Clock and Data Recovery
The receive CDR circuit follows the CTLE and works in tandem with the DFE. The receive CDR PLL can
lock onto the input reference clock or the incoming data stream to be able to re-time the incoming data.
The deserializer is closely coupled with the CDR, and translates the data from a serial to a parallel
stream.
3.1.1.6.1 CDR Options
The PMA of each lane includes a PLL used for the receiver CDR. The CDR PLL supports
lock-to-reference and lock-to-data modes, which allows customization of the CDR options best suited for
the application. It also includes a Burst-mode receiver option, which can switch between both options
that are selectable through the Libero transceiver configurator.
Lock-to-Reference: The phase frequency detector (PFD) in the CDR tracks the receiver input reference
clock. The PFD controls the charge pump that tunes the VCO in the CDR. The LOCK status signal is
asserted high to indicate that the CDR has locked to the phase and frequency of the receiver input
reference clock regardless of the data phase detector (PD). Lock-to-reference is used to lock the
transceiver CDR to the reference clock rather than the incoming data when the receiver is used as a
simple over-sampler, or when the CDR must be locked to a local oscillator.
Lock-to-Data: The CDR must use the lock-to-data mode to recover the clock and data from the incoming
serial data. In this mode, the data phase detector of the CDR tracks the incoming serial data at the
receiver input. Depending on the phase difference between the incoming data and the CDR output clock,
the PD controls the CDR charge pump that adjusts the VCO. The LOCK status signal is asserted when
the CDR finds valid data. The actual lock time depends on the incoming data stream's transition density.
Burst Mode Receiver: The transceiver CDR circuit has enhanced capabilities to support burst mode
receivers (BMR). BMR is used in NGPON2 and 10GEPON passive optical network applications for fast
and bounded lock times. The BMR option is used to implement the fast clock-data recovery when the
conventional bang-bang phase detector PLLs cannot meet the stringent lock times required by the
passive optical network (PON) applications.
Note: DFE auto-calibration is not available when the transceiver is configured for burst mode (BMR).
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