Revision History
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 1
1 Revision History
The revision history describes the changes that were implemented in the document. The changes are
listed by revision, starting with the current publication.
1.1 Revision 9.0
The following is a summary of the changes in this revision.
• Information about incremental DFE calibration was added. See DFE Calibration, page 12.
• Information about Enhanced Receiver Management, page 16 was updated.
• Information about Transceiver Reference Clock Interface, page 61 was updated.
• Information about spread spectrum was updated. See Table 28, page 90.
• Information about PIPE Port List, page 39 and PMA Port List, page 46 was updated.
• Information about Loss of Signal Detect (LOS), page 9 was added.
• Information about PMA and PCS Resets, page 73 was updated.
• Information about Transceiver Reference Clock Configurator, page 82 was updated.
• Information about Dynamic Reconfiguration Interface, page 124 was updated.
• Information about Jitter Attenuator, page 63 was updated.
• Information about Transceiver Initialization, page 107 was updated.
• Information about Libero Generated Files, page 101 was updated.
1.2 Revision 8.0
The following is a summary of the changes in this revision.
• Information about 8b10b Data Path Interface, page 24, 8b10b Bit and Octet Sequencing, page 25,
and 8b10b System Registers, page 26 was added.
• Information about 64b6xb Data Path Interface, page 30, 64b6xb System Registers, page 32,
64b66b Receiver, page 33, 64b66b Transmit, page 34, 64b67b Transmit, page 35, and 64b67b
Receive, page 35 was added.
• Information about None_DFE (Static DFE) was updated. See Enhanced Receiver Management,
page 16.
• Information about LANE#_CLK_REF port name was added. See Table 7, page 27, Table 11,
page 36, Table 12, page 39, and Table 13, page 46.
• Information about Table 21, page 68 was updated.
• Information about DFE Coefficients, page 104 was added.
• Information about AC/DC Coupled Connection, page 110 was updated.
• Information about Table 39, page 125 was updated.
• Information about Design for Protocols, page 127 and Unused Transceiver Pins, page 129 was
updated.
• Information about Half-Duplex Mode, page 100 was updated.
• Information about Receive Input Buffer, page 8 was updated.
1.3 Revision 7.0
The following is a summary of the changes in this revision.
• Information about physical constraint instances was updated. See Table 34, page 103.
• Information about TX and RX interface clock was updated. See Table 16, page 54.
• Information about Enhanced Receiver Management, page 16 was updated.
1.4 Revision 6.0
The following is a summary of the changes in this revision.
• Information about capability to support switching between two TXPLLs or two CDR REFCLKs via the
DRI interface was added. See Transceiver Interface Configurator, page 91.
• Information about LiteFast was updated. See Table 1, page 4.
• Information about PCS/FPGA Fabric Interface, page 48 was added.
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