Implementation
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 94
Preset configurations are available within the Transceiver Interface Configurator to speed up the
transceiver configuration. Factory provided presets are available with the Libero release. Additionally,
customized presets can be saved. See Transceiver Modes, page 99 for more information.
3. Select Number of lanes from 1 to 4 in the general settings configuration.
4. Enter the Transceiver data rate and select one of the TX clock division factors. The TX PLL base
data rate is calculated in the GUI. The calculated TX PLL base data rate must be entered under the
desired output clock option inside the PF_TX_PLL configurator. LANE#_TX_PLL_REF_CLK_#,
LANE#_TX_BIT_CLK_0, and LANE#_TX_PLL_LOCK_# are included in CLKS_FROM_TXPLL_#
BIF (bus interface). This connection is required between the TXPLL and Transceiver Interface.
5. Select the desired CDR reference clock mode and CDR reference clock frequency from the
drop-down list based on the application.
Note: CDR reference clock frequency drop-down list is populated with valid frequencies based on the data
rate.
6. Select the CDR reference clock source based on the design requirements. The dedicated clock
adds a dedicated CDR_REF_CLK port whereas the fabric port only includes a port that can be
2. TX_CLK_G/R frequency = RX_CLK_G/R frequency = FPGA Interface frequency = data rate/(PMA-PCS width × PCS Gearing).
Table 32 • Clocks and Resets
Interface Options Options Default Details
Interface clock Use as PLL reference clock Disabled When Use as PLL reference clock is selected,
this exposes additional ports that permit
connection to the PLL REFCLKs.
LANEn_TX_CLK_TO_PLL_REFCLK
LANEn_RX_CLK_TO_PLL_REFCLK
This allow designs that require gearing other than
2:1 with wider fabric interfaces and use dedicated
routing to the PLL. This is used in place of
CLKDIV, which does not have the dedicated
routing to PLL.
TX clock Global, Regional,
Regional (Deterministic),
Global Shared
Regional See Table 16, page 54
RX clock Global, Regional,
Regional (Deterministic),
Global Shared, and NA
Regional NA option must be selected when the PCS is
configured in Soft PIPE mode (PCIe). See
Table 16, page 54
Interface Resets PMA Reset
1
TX and RX
PCS Reset Tx Only, Rx
Only, Tx and
Rx
RX Only – only RX side can be reset from the
fabric.
TX Only – only TX side can be reset from the
fabric.
TX and RX – both RX and TX sides can be reset
from the fabric.
Optional Ports Enable/Disable TX_BYPASS port/TX_ELEC_IDLE port.
See Table 11, page 36 or Table 13, page 46.
RX_READY_CDR and RX_VAL_CDR ports.
See Enhanced Receiver Management, page 16.
JA_CLK port. See Jitter Attenuator, page 63.
Dynamic
Reconfiguration
Enable Dynamic
Reconfiguration Interface
(DRI)
Disabled
1. The minimum pulse width required is 16 clock cycles.
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