Overview
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 6
2.1 Features
The PolarFire transceiver enables users to quickly build high-speed links that support many standard
protocols with the features listed:
• Supports data rates from 500 Mbps (250 Mbps with interpolation) up to 12.7 Gbps.
• Serialization/deserialization width at FPGA fabric interface—8, 10, 16, 20, 32, 40, 64, and 80 bits.
• Differential output termination from 85 , 100 , and 150
• Low-power modes.
• Receivers are compatible with CML and LVDS I/O Standards.
• Transmitters are compatible with CML, LVDS, and LVPECL I/O Standards.
• Configurable transmit pre- and post-tap de-emphasis controls.
• Configurable amplitude control from 250 mV to 1 V differential.
• Receivers detect circuitry for use with PCIe.
• Out-of-band (OOB), electrical idle signaling capability for
• Serial-attached SCSI: small computer system interface (SAS).
• Serial advanced technology attachment (SATA).
• Peripheral component interconnect express (PCIe).
• Spread-spectrum generation built into the transmit phase-locked loop (PLL).
• 1 Gb and 10 Gb SyncE compatible Jitter attenuation available in the transmit PLL for loop timing
applications.
• Continuous time linear equalizer (CTLE) with optional auto-calibration to improve received signal
integrity.
• 5-tap decision feedback equalizer (DFE) with auto-calibration to compensate for high-frequency
losses.
• Receive data eye monitor for link analysis.
• Configurable peak detector/signal detect.
• Polarity inversion (receiver).
• Diagnostic loopback modes.
• Embedded pseudo-random binary sequence (PRBS) test pattern generators/checkers—available
PRBS polynomials (2
n
), where n = 7, 9, 15, 23, and 31.
• AC JTAG (IEEE 1149.6) and DC JTAG (IEEE 1149.1) transmitter and receiver.
• IBIS-AMI support of transceiver inputs and outputs
• Supports AC and DC coupling modes with configurable transmit common-mode voltage.
• Embedded PCS:
• 8b10b—encoding/decoding is provided.
• 64b6xb—64b/66b or 64/67b encoding/decoding with gearbox logic is provided.
• PIPE—PHY interface for the PCI Express Rev 3.0 supporting PCIe Gen1/2.
• PMA only—direct access to the PMA without any encoding.
• PCIe—fully embedded PCIe Gen1/Gen2 root-port or endpoint subsystem (PCIESS) with AXI4
user interface with built-in DMA. The embedded PCIe controller subsystem is available only
within Quad0. See UG0685: PolarFire FPGA PCI Express User Guide for more information on
the embedded PCIE capabilities and its usage.
The Microsemi Libero
®
SoC software supports configuration for the various modes of transceiver
operations. Table 1, page 4 shows which of these configurations support industry-standard protocols and
user-defined custom protocols. The Libero SoC software design tools allow designers to set the
configuration needed for a specific operational mode for each transceiver lane. The software correctly
provisions and generates all the required programming and configuration data used to initialize and bring
the transceiver into operation. The transceiver configuration registers are set automatically by the Libero
SoC transceiver configurator. These registers must be left at their default values set by the configurator,
except for use cases that explicitly request different values.
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