Functional Description
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 61
3.5.4 Transceiver Clocks
The transceiver transmitters have high-performance bit clocks running at half the line rate of the fastest
transmit lane driven by the clock. The transmit PLLs generate these clocks based on a transmit
reference clock, with the configuration set in the Libero design software.
Within each lane, the transmit bit-rate clock (Figure 6, page 14) is divided by 1 (full rate), 2, 4, 8, or 11 to
set the transmit rate of a given lane. The resulting clock is further divided by 8, 10, 16, 20, 32, 40, 64, and
80 to generate a parallel transmit word clock to the fabric.
The transceiver receivers have their own per-lane receive PLL built into the CDR to generate a per-lane
receive clock supporting asynchronous data in that lane. Generally, the CDR is used in lock-to-data
mode. The receive CDR PLL initially spins up to approximate the correct frequency to lock to the
incoming data by first locking to an input receive reference clock that is near the incoming data rate.
Once that is achieved, it then switches to clock recovery mode where it locks to the incoming data and
then extracts the clock from the incoming data (which is also a half-rate bit clock running at half the
speed of the received data rate). Lock-to-reference is also available for customized protocols. The CDR
PLL locks to the local input reference clock and spins to the desired frequency without performing phase
compensation or clock recovery functions. These applications pass the data directly to fabric where it can
be used for custom over-sampling and synchronizing processing.
The per-lane CDR extracts a clock from the incoming data stream and then generates a receive parallel
word clock that is divided by 8, 10, 16, 20, 32, 40, 64, or 80 from the bit rate of the given lane.
3.5.4.1 Transceiver Reference Clock Interface
The reference clock interface block to the transceiver provides multiple options for supplying the
reference clock input to the transceiver transmit and receive PLLs (Figure 43, page 62). Various sources
can provide the reference clock interface via REFCLK0 and REFCLK1 ports.
• Differential dedicated input pad: allows a direct clock input of a low-jitter reference clock via a
LVDS/HCSL input pins REFCLK_P/N.
• Single-ended dedicated input pad(s): allows the selection from two different single-ended clock
inputs, enabling the transmit PLL to select from two different clock sources. Separate single-ended
clock inputs allow unrelated transmit and receive clock sources to be sourced to the transceiver.
Note: Two separate single-ended inputs allow one for the transmit reference clock and a second for the receive
reference clock.
• Cascade of a reference clock: the clock received on the external pins of a quad can be driven to
the quad below. The reference clock interface provides cascading of an input reference clock path
from the REFCLK pins of one transceiver quad to the TxPLLs and receiver CDRs of other
transceivers. In designs that have lanes spanning different transceiver quads, the cascading clocks
eliminate the need to connect the on-board reference clock sources to the REFCLK pin of each
transceiver quad. The reference clock interface also drives a clock signal on the REFCLK pins to the
clock logic in the FPGA fabric.
• Recovered clock: allows for the reference clock to be sourced by the recovered clock from local
quad (via JA_REF_CLK). Within a Quad, the recovered clock used as JA_REF_CLK has dedicated
connections between the lanes without any additional jitter.
For inter-quad or using the recovered clock from one Quad to the JA_REF_CLK of another Quad,
this has added jitter from using routing of the FPGA fabric. Since this clock is from the noisy digital
VDD/VSS domain on the device, the reference clock jitter is higher than the dedicated inputs.
Generally used with the jitter attenuation feature.
Note: The reference clock driving the transmit PLL REF_CLK also serves each lane for the receive CDR. Since
each receive lane has an independent PLL, it is possible to use an independent reference clock per
receive lane. PLL for the CDR is per transceiver PMA lane.
The PF_XCVR_REF_CLK does allow the FAB_REF_CLK output pin to drive a fabric global resource.
This connection is limited to one per quad and if used, it prevents using the global of a XCVR lane in the
same quad. However, you can connect XCVR_ FAB_REF_CLK output pin to PLL and one lane to global
at the same time. For information about implementation of this connection, see Transceiver Reference
Clock Configurator, page 82.
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