Functional Description
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 39
The PIPE interface is used by the embedded PCIESS or can be used with a soft PCIe IP in the FPGA
fabric. The embedded PCIESS is accessed through a dedicated interface to the PIPE interface mode,
which ties the PCIESS to the PIPE without additional fabric logic. All PHY interface signals are
synchronous to the PIPE CLOCK. The PIPE PCS is used as the interconnection between either the
embedded PCIe block or used with a fabric-based soft-IP connected to the transceiver PMA. The port list
differs slightly based on whether the PIPE interface is configured in PCIe mode. See the PHY Interface
for the PCI Express.
Table 12 • PIPE Port List
Port Name Direction Clock Description
LANE#_CDR_REF_CLK_#/LA
NE#_CDR_REF_CLK_FAB
Input Reference clock to lane CDR. Can be sourced from
either FPGA clock or from a
XCVR_#[A,B,C]REFCLK_P/N pin.
LANE#_CLK_REF Input This port is exposed to user with Half-Duplex option.
LANE#_REF_CLK must be connected by the user to a
stable clock with same clock frequency as Recovered
clock such as the local clock.
LANE#_TX_PLL_REF_CLK_# Input Input clock from TX_PLL REF_CLK_TO_LANE output
pin. Included in CLKS_FROM_TXPLL_# BIF (bus
interface).
LANE#_TX_PLL_LOCK_# Input Input lock status from TX_PLL LOCK output pin.
Included in CLKS_FROM_TXPLL_# BIF (bus interface).
LANE#_TX_BIT_CLK_# Input Clock from BIT_CLK of the XCVR TXPLL. Included in
CLKS_FROM_TXPLL_# BIF (bus interface).
LANE#_TX_DATA[39:0] Input Parallel data bus to the PCS from the fabric. The
PF_XCVR send/receive order is low to high byte.
When the hard PCIESS is used, received data is always
32 bits wide. The upper bits [39:32] are ignored.
When the soft PCIe IP design is used, then TXDATA is
40 bits wide; otherwise, it is 32 bits wide (the upper byte
is ignored).
LANE#_TXDATAK[3:0] Input TX_CLK_[R:G] Indicates the type of characters on the TXDATA bus. A 0
indicates a data character, while 1 indicates a control
character. If the soft PCIe IP is used, this signal is
ignored.
LANE#_TXDETECTRX_LOOP
BACK
Input TX_CLK_[R:G] High instructs the PHY to begin the receive detect
process or external loopback as described in the PCI
Express specification. As with many PIPE signals, the
meaning of this signal depends on which power state the
PHY is in. When in P1 state, this signal informs the PHY
to perform a receive detect, but when in P0 state, this
signal informs the device to go into loopback mode.
TXCOMPLIANCE Input TX_CLK_[R:G] When asserted, this ordinarily forces the currently
running disparity to negative. As the name implies, this is
useful in conjunction with the transmission of the
compliance pattern to generate test data. It is also used
in a multi-lane implementation to turn off any unused
lanes, for example, when a ×4 link must operate as a ×1.
When both TXCOMPLIANCE and TXELECIDLE are
asserted, the affected lane turns off to conserve as much
power as possible.
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