Implementation
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 100
Full-duplex configures the XCVR with common Tx and Rx data rates. Although, users can see
independent control for data rate and PCS-Fabric widths, a Libero SoC DRC prevent users from
selecting different rates/widths when TX and RX is in full-duplex mode. In full-duplex mode, the user
must match the Rx and Tx requirements.
4.2.2 Half-Duplex Mode
Another mode of the transceiver is half-duplex mode. It is defined by allowing parts of the Rx and Tx to
operate independently. Half duplex modes optimize the use of lanes within XCVR quads by allowing the
separation of Rx and Tx within a lane. To address the half-duplex modes, the following options are
available to transceiver.
• Tx only
• Rx only
• Tx and Rx (Independent)
When users select Tx only or Rx only option, then one physical XCVR lane is completely used, and the
un-used Rx or Tx cannot be used. When user select Rx only in the GUI, the Tx GUI options is marked as
N/A for display purposes. In the same way, when user select Tx only in GUI, the Rx GUI options is
marked as N/A for display purposes. However, in both cases, the un-used Tx or Rx parameters are still
set to some valid values in the generated core (based on the default parameter values from core).
PMA_ARSTN resets both the Tx and Rx of the PMA, however, the PCS_ARSTN will reset the TX only or
Rx only accordingly.
If users intend to implement two independent half-duplex channels in the same physical XCVR lane then
select the 'Tx and Rx (Independent)' option in Transceiver mode. By using 'Tx and Rx (Independent)'
option, users can specify a different data rate for RX channel and TX channel. When configured Tx and
Rx (Independent), an additional input pin (LANE#_CLK_REF) is exposed on the component. See the
related port list for pin definition. Additionally, the PCS-FABRIC width can also be different between RX
and TX. However, if half-duplex applications are to be merged into one XCVR lane, then both
applications must use the same basic mode of the PCS. The reason for this is, system register control for
steering the data path among the four basic modes (PIPE, 64B6xB, 8B10B, NATIVE/PMA) is shared for
TX and RX.
Libero SoC programs the appropriate registers within the transceiver to power-down the serializer or de-
serializer in Tx only /Rx only Transceiver modes.
Tx only, Rx only, and Tx and Rx (Independent) modes are supported only in PMA mode. In 8b10b mode,
both Tx and Rx must use the same fabric interface width. Tx/Rx Independent option PCS mode applies
for both Tx and Rx and cannot be different within the lane. For example, the Tx cannot be 8b10b when
the Rx is 64b66b.
The TXPLL supports Fractional-N frequency synthesizer, and the CDR PLL only supports integer-based
synthesis. Typically, the same REFCLK is used for both the TXPLL and CDR PLL for full-duplex lane.
The user has the option to use integer-based for the TXPLL if the frequency is achieved without issue.
If the TXPLL uses Frac-N rather than integer-based to synthesize the bit clock, the CDR PLL will not
have the Frac-N capability. Consequently, the user needs to determine if the PPM tolerance of the CDR
is enough to compensate for the TXPLL rate.
Table 33 • PCS Modes Supported
Transceiver Mode PCS Mode supported
Tx and Rx (Full Duplex) PMA, 8b10b, 64b6xb, PIPE
Tx only PMA and 8b10b
Rx only PMA and 8b10b
Tx and Rx (Independent) PMA mode
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