Microchip Technology Microsemi UG0677 - Table 21 Reference Clock Input Buffer Standards

Functional Description
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 68
Users need to be aware of power supply requirements and voltage reference requirements. See
UG0686: PolarFire FPGA User I/O User Guide for more information.
3.5.4.3.5 Reference Clock Input Pins
The input pins XCVR_REFCLK_P/N are assigned through the Libero transceiver configurator based on
the targeted transceiver quad. The pins are identified based on quad. For example, where there are
three transmit PLLs:
• XCVR_#A_REFCLK_P/N—This REFCLK input is associated with the connection dedicated to the
TXPLL_SSC. Also, this input has connectivity to the Global clock resource.
• XCVR_#B_REFCLK_P/N
• XCVR_#C_REFCLK_P/N (this input is only available in a subset of transceiver quads per device as
shown in Figure 52, page 71 and Figure 53, page 72)
The following figure shows REFCLK input pins. These pins drive into the reference clock interface block
to the TxPLLs and CDRs per quad or cascaded among several quads as required by the user design.
Table 21 • Reference clock input buffer Standards
1
Single ended Differential
2
Reference voltage (Not supported
for ES/XT devices).
LVCMOS18 (VDDI = 2.5) HCSL25
3
HSUL18I (VDDI = 2.5)
LVCMOS25 (VDDI = 2.5) LVDS25 HSUL18II (VDDI = 2.5)
LVCMOS33 (VDDI = 3.3) LVPECL33 (VDDI = 3.3) SSTL18I (VDDI = 2.5)
LVTTL (VDDI = 3.3) MINILVDS25 SSTL18II (VDDI = 2.5)
MIPI25 SSTL25I (VDDI = 2.5)
MLVDS25 SSTL25II (VDDI = 2.5)
PPDS25
RSDS25
SLVS25
SUBLVDS25
LVDS33
4
1. VDDI = VDD_XCVR_CLK
2. Differential inputs do not include internal voltage-bias circuitry.
3. LP-HCSL is supported with HCSL25 reference clock setting without 100  differential ODT.
4. LVDS33 is supported in device with VDDI= 3.3 V and supported in Libero by selecting LVDS25 IO Standard configuration.