Functional Description
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 48
3.4 PCS/FPGA Fabric Interface
The FPGA fabric-transceiver interface includes both clock and data signals. This interface provides clock
interconnects using the global or regional clock networks in the FPGA fabric. Based on the transceiver
lane configuration, the receive parallel output clock is recovered from either the receive serial data or the
rate matched clock generated by the embedded clock domain crossing logic. Transmit output is always
from the TxPLL. The PCS/FPGA fabric can gear the fabric interface by an additional 1:2 ratio provided by
the PCS dividers (see Transmit PCS Divider, page 15). The modes where this can occur are 8b10b using
8-octet interfacing, 64b6xb using 8-byte interfacing, PMA mode 64-bit, and 80-bit interfacing.
Local clock outputs of the PF_XCVR are programmed to track with the additional gearing done in the
PCS. If the fabric interface width is geared by the PCS and global clocks are the source of the interface
timing, then the global clock output must be divide-by-two.
There are four clocking resources from PCS to the fabric-Global, Regional, Regional (Deterministic), and
Global-Shared.
• Global: These clocks have a dedicated interconnection specifically designed to reach throughout
the device from the transceiver fabric interface onto dedicated FPGA fabric global clock network.
Global clocks are designed to have low skew and low duty cycle distortion, low power, and improved
jitter tolerance and support for very high-frequency signals.
LANE#_RX_READY
2
Output Lane#_ RX_READY = 1 means the Rx PLL is
locked. LANE#_RX_READY rises when the
enhanced receiver management and CDR
completes a fine lock detection to the incoming data
transitions and the de-serializer is powered-up. If
there is no incoming data to the CDR then the
RX_READY is low. The primary purpose of this pin
is communicating to fabric that the CDR is locked to
serial input data and is producing valid clocking.
Note: In a loopback case while looping the local
transmitter output to the receiver input, it is
necessary to take the Tx out of reset to ensure valid
serial transitions, allowing the Rx CDR to lock. The
system deadlocks, if the user waits till Rx CDR locks
before the Tx is released from reset.
LANE#_RX_IDLE
2
Output Receives electrical-idle detection flag.
LANE#_Rx_IDLE peak detector logic is only valid
for a limited minimum density of transitions on the
Rx data and not to be used in applications above
5Gbps. Enhanced Receiver Management can
provide a reliable mechanism for higher data rates.
LANE#_RX_CLK_[R:G]
2
Output Global or regional receive clock to fabric.
LANE#_TX_CLK_[R:G]
2, 3
Output Global or regional transmit clock to fabric.
LANE#_TXD_N
2
Output Transceiver transmitter differential output.
LANE#_TXD_P
2
Output Transceiver transmitter differential output.
1. N can be 7, 9, 15,19, 31, 39, 63, and 79.
2. LANE# can be 0, 1, 2, and 3.
[R:G] naming is generated based on the use of regional or global resources that are selected with Libero.
3. In the MPF500 devices, the TX_CLK_R and RX_CLK_R pins of XCVR lanes placed in the PCIESS(Q0) and GPSS1(Q1) quads
cannot drive I/Os.
Table 13 • PMA Port List (continued)
Port Name Direction Clock Description
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