Microchip Technology Microsemi UG0677 - 3 Functional Description; Pma; Receiver

Functional Description
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 7
3 Functional Description
The PolarFire transceiver (Figure 1, page 5) is divided into four distinct transmit (Tx) and receive (Rx)
blocks:
• PMA
• PCS interface block, including a dedicated PCIe PCS
• Transmit PLL (Tx PLL)
• Reference clock inputs
The high-speed PMA blocks connect to the FPGA fabric through the PCS block. The PMA generates the
required clocks and converts the transmit data from parallel to serial, and receive data from serial to
parallel. Each PMA block includes a connection to a PCS block and associated interface to the FPGA
fabric making up a transceiver lane. The PCS interface block provides several industry-standard
interfaces for use in protocol-specific designs.
A group of four transceiver lanes is called a quad. Each quad has a local transmit PLL used exclusively
within the four transceiver lanes. Additional transmit PLLs are shared between quads.
In addition to the 8b10b, 64b6xb, PIPE, and PMA only blocks, two PCIe PCS logic blocks are included in
each PolarFire device. These blocks include hard embedded logic that provides full-featured PCIe
endpoint/root port sub-system. These PCIe subsystems (PCIESS) have hard connections to multiple
transceiver lanes, providing flexibility for ×1, ×2, and ×4 width links. See UG0685: PolarFire FPGA PCI
Express User Guide for additional information pertaining to PCIe.
3.1 PMA
The transceiver lanes include PMA receiver and transmitter sub-modules. These PMA sub-modules
include the input and output buffers, signal conditioning circuits, CDRs, and transceiver. The PMA
architecture allows the receive and transmit portions of each lane to operate independently. The PMA
features are initialized at power-up and can also be altered during device operation using an APB
dynamic reconfiguration interface (DRI).
The SmartDebug tool set provides access to dynamic changes of PMA features, including transmit and
receive tuning, and receive eye monitoring capabilities.
3.1.1 Receiver
The receiver deserializes high-speed serial data received through the input buffer by creating a parallel
data stream for the FPGA fabric and recovering the clock information from the received data. The
receiver portion of the PMA includes the receiver buffer, the clock and data recovery (CDR) unit, and the
deserializer. The deserializer within the receive PMA passes deserialized data to the PCS block across a
data bus up to 40-bits wide of the PMA-PCS interface, which provides the data path to the gearing logic
before the data is passed to the FPGA fabric.