Debug and Testing
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 122
7 Debug and Testing
PolarFire FPGA include debug and testing features for multi-gigabit transceivers. It provides capabilities
for diagnostic test setups and inserting test patterns during FPGA testing and debugging. This chapter
describes the embedded transceiver capabilities that allow high-speed link diagnostics.
7.1 PRBS Generator/Checker
Each PolarFire FPGA transceiver has embedded blocks with a built-in PRBS generator and checker that
can be used to perform link testing and diagnostics. These test capabilities are available to the user
through the SmartDebug toolset. For more information on PRBS generator and checker, see
SmartBERT, page 117.
The implementation of the PRBS generator uses a linear feedback shift register (LFSR). The generator
produces a pre-defined sequence of 1s and 0s, occurring with the same probability. A sequence of
consecutive n × (2
n -1
) bits comprise one data pattern, and this pattern repeats itself over time. This
sequence is compared within the checker to ensure no errors in the sequence are detected.
The PRBS generator/checker supports the following test patterns for 32- and 40-bit wide PMA parallel
buses.
• PRBS31: x
31
+ x
28
+ 1
• PRBS23: x
23
+ x
18
+ 1
• PRBS15: x
15
+ x
14
+ 1
• PRBS9: x
9
+ x
5
+1
• PRBS7: x
7
+ x
6
+ 1
PRBS7 is also supported in widths of 8, 10, 16, and 20 bits.
Note: Some PRBS pattern polynomials are used as part of several standards such as ITU-T recommendations.
The PRBS7 polynomial is not necessarily a telecommunications standard but is typically used by test
equipment because its similarity with 8b10b-encoded patterns.
7.2 Loopback
There are three loopbacks supported within the transceiver blocks to assist designers in debugging the
system by segmenting the link (Figure 100, page 123). The loopbacks are accessed through the
SmartDebug tools. For information about data rate performance of loopback paths, see PolarFire FPGA
Datasheet.
7.2.1 EQ Far-End Loopback
Far-end serial loopback (receiver to transmitter) or EQ FELB bypasses all input equalization (CTLE and
DFE) as detailed in Receiver, page 7 and therefore, only supports lower speed operation since these
features cannot be utilized.
Because it does not use the CDR (the receive and transmit lanes are essentially shorted together), there
is no PPM relationship between the receive and transmit data.
7.2.2 EQ Near-End Loopback
Near-end serial loopback (transmitter to receiver) or EQ NELB uses the digital serialized transmit data
that bypasses the transmit output buffer and loops the data back to the third-stage CTLE input, bypassing
the receiver input and connecting to the CDR only.
The EQ NELB mode does not test the transmit buffer, high-speed receive buffer, low-speed receive
buffer, CTLE stages 1 and 2 for the CDR, CTLE stages 1, 2, and 3 for the DFE and eye monitor circuits.
7.2.3 CDR Far-End Loopback
CDR FELB (CDR far-end loop back), occurs after the parallel word creation in the PCS through a
loop-back FIFO. The transmit word is then serialized and sent out of the transmitter.
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