Functional Description
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 38
Note: LANE# can be 0, 1, 2, and 3. [R:G] naming is generated based on the use of regional or global resources
that are selected with Libero.
3.3.3 PIPE
The transceiver PMA interface to PCIe is based on a standard PIPE interface logic. It provides a
standard interface between the PMA lane and the higher link-level of the PHY. The logic handles the
following functions:
• 8b10b encoding/decoding logic.
• Lane polarity requirements.
• Elastic FIFO and SKP character logic.
• Hot-plug insertion logic.
• PMA controls required by PCIe standard.
• PCIe detection of remote receiver, power state change, and so on. Provides translation of MACs
LTSSM states into PMA power states.
LANE#_RX_READY Output Rises when the enhanced receiver management and
CDR completes a fine lock detection to the incoming
data transitions and the de-serializer is powered-up. If
there is no incoming data to the CDR then the
RX_READY is low. The primary purpose of this pin is
communicating to fabric that the CDR is locked to
serial input data and is producing valid clocking.
Note: In a loopback case while looping the local
transmitter output to the receiver input, it is necessary
to take the Tx out of reset to ensure valid serial
transitions, allowing the Rx CDR to lock. The system
deadlocks, if the user waits till Rx CDR locks before
the Tx is released from reset.
LANE#_RX_IDLE Output Receive electrical-idle detection flag.
LANE#_Rx_IDLE peak detector logic is only valid for
a limited minimum density of transitions on the Rx
data and not to be used in applications above 5Gbps.
LANE#_TX_CLK_STABLE Output Transmit transceiver/PCS lane ready flag.
LANE#_RX_CLK_[R:G] Output Global or regional receive clock to the fabric for the
receiver.
LANE#_TX_CLK_[R:G]
1
Output Global or regional transmit clock to the fabric for the
transmitter.
LANE#_STATUS_HI_BER Output RX_CLK_[R:G] From the bit error rate monitor, which counts bad sync
header values (0b00 or 0b11). Occurs over 125 µs
interval.
LANE#_STATUS_LOCK Output RX_CLK_[R:G] From the selected receive sync lock state-machine
(Clause 49 or Clause 82). This is 0 when the sync
header boundary is not locked, and it is 1 when sync
lock is achieved. See IEEE 802.3 Clause 49 and
Clause 82 for block lock state machine.
LANE#_TXD_N Output Transceiver transmitter differential output.
LANE#_TXD_P Output Transceiver transmitter differential output.
1. In MPF500 devices, the TX_CLK_R and RX_CLK_R pins of XCVR lanes placed in the PCIESS(Q0) and GPSS1(Q1) quads
cannot drive I/Os.
Table 11 • 64b66b/64b67b Port List (continued)
Port Name Direction Clock Description
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