Functional Description
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 37
LANE#_TX_ELEC_IDLE Input Asynchronous Transceiver configurator allows pin to be exposed on
component. This input forces XCVR_P/N transmit
output pad pair to a common-mode voltage. It is used
for low-frequency out-of-band signaling, or to signal
entry into a low-power state to the link partner.
LANE#_TX_BYPASS_DATA Input Asynchronous Transceiver configurator allows pin to be exposed on
component. When LANE#_TX_BYPASS_DATA=1,
the data can be driven into the transmit pads instead
of the normal serializer data. The bypass is
asynchronous and this signal does not transit through
the FWF. This pin should be tied low if exposed to
fabric and not used.
LANE#_RXD_N Input Transceiver receiver differential input.
LANE#_RXD_P Input Transceiver receiver differential input.
LANE#_RX_HDR_VAL Output RX_CLK_[R:G] Enable for header data in
LANE#_RX_SOS Output RX_CLK_[R:G] Start-of-sequence pulse for a super frame, the length
of which varies based on the mode. High output
indicates start of sequence.
LANE#_RX_DATA_VAL Output RX_CLK_[R:G] Valid when there is data on RX_DATA.
LANE#_RX_HDR[3:0] Output RX_CLK_[R:G] Sync header corresponding to different encoding
types.
LANE#_RX_DATA[63:0] Output RX_CLK_[R:G] Receive encoded data from 64b6b to the fabric.
PF_XCVR sends/receives bytes in high to low byte
order only in the 64B6xB mode.
Bit 31 or bit 63 arrives first in the serial data.
LANE#_RX_VAL Output RX_CLK_[R:G] LANE#_RX_VAL indicates that the XCVR data path is
initialized. The parallel bus of LANE#_RX_DATA[N:0]
contains actual data recovered from the serial stream
when LANE#_RX_VAL = 1.
In 64b66b/64b67b mode, the Rx PCS logic self-resets
when the CDR is not locked. In this mode,
LANE#_RX_VAL rises just after LANE#_RX_READY
rises. If you want to control Rx PCS reset, hold
LANE#_PCS_ARST_N in reset when
LANE#_RX_READY is low and release, when
LANE#_RX_READY goes high. Once
LANE#_PCS_ARST_N is released from reset,
LANE#_RX_VAL rises to indicate the Rx parallel data
is valid. In 64b6xb mode, the RX_VAL is qualified
when the XCVR receiver calibration completes,
included with the enhanced receiver management
completion, and the CDR locks.
Table 11 • 64b66b/64b67b Port List (continued)
Port Name Direction Clock Description
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