Signal Integrity Conditioning
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 109
Building a transceiver based design using Libero SoC software flow allows flexibility to improve the
PolarFire transceiver performance within the system. The PolarFire software sets initial good defaults for
the user's custom design based on input information to the transceiver configurators. The user can
change the associated transceiver input and output settings using the IO Editor after initial design
generation. The user can further enhance the signal integrity qualities of the PolarFire transceiver after
design place, route, and bitstream generation by using the SmartDebug capabilities. This allows user to
continue the signal integrity tuning after programming the device in the system and provides a feedback
path to include the customized signal integrity settings in subsequent design regeneration.
Both the Signal Integrity views of the PolarFire IO Editor and SmartDebug Transceiver present the same
signal integrity settings for both the transmitter and receiver. The available settings are predefined by the
factory providing a flexible means to adjust the XCVR.
5.1 Transmitter
The transmitter takes parallel data from the FPGA fabric through the PCS-fabric interface block and
gearing logic. The data passes through the PMA-PCS interface to the serializer to create a high-speed
serial data stream using the serial clock provided from the transmit PLL. For more information about
transmitter, see Transmitter, page 14.
5.1.1 Transmit Emphasis and DC Amplitude
Transmit emphasis and DC amplitude settings adjust the transmitter output drivers. The settings are
provided from a drop-down menu of pre-defined combinations of Tx emphasis and DC amplitude.
The DC amplitude is adjusted by changing the driver segments to deliver a differential swing to the
receiving device. The trade-off between large output-swing is power consumption and output return loss.
The transmit emphasis adjusts the magnitude of the output based on the prior bit values reducing the
successive bits. This transition emphasis compensates for the channel losses and opens the signal eye
at the far-end receiver. This is accomplished by deemphasizing or weighting driver taps with negative dB
adjustment.
Adjustment of the Tx amplitude and Tx emphasis are used to match the PCB interconnect losses. For
information about Predefined Transmit Emphasis and DC Amplitude settings, see AC483: PolarFire
FPGA Transceiver Signal Integrity Application Note.
5.1.2 Impedance (Differential)
This feature is used to add—85 or 100 or 150 —calibrated internal impedances onto the
differential outputs. This setting adjusts the impedance selected to match the system to optimize
performance.
5.1.3 Tx Insertion Loss
Table 35, page 109 lists the recommended transmit amplitude and emphasis values for short, medium,
and long applications. User should manually adjust the amplitude/emphasis to match the Tx channel of
the PCB. For Rx, these values can be set in Libero.
5.1.4 Transmit Common Mode Level
Transmit common mode level is used as a percentage—50% or 60% or 70% or 80%—of full common
mode level or VDDA. It is only adjusted when DC coupled (for example with SDI or high CID protocols).
This is to match the common-mode restoration to the DC coupled receiver. For AC coupled systems, the
level should remain as default.
Table 35 • Amplitude and Emphasis
Channel Type Amplitude (mV) Emphasis (dB)
Short 400 -3.5
Medium 800 -6
Long 1000 -6
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