Microchip Technology Microsemi UG0677 - Loss-Of-Signal Detector; Polarity Invert; IO Editor for Signal Integrity; Table 36 LOS Range

Signal Integrity Conditioning
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 111
5.2.5 Loss-of-Signal Detector
Loss-of-signal (LOS) detector (low and high value) sets the requirement of the voltage detector. The
following table lists the upper and lower set points for a LOS to ensure that a good signal is applied into
the receiver. Referring to data sheet Loss-of-Signal detect, Peak Detect Range (VDETLOW), below the
Peak Detect Range minimum value setting is interpreted as “no signal” and above the maximum number
will interpreted as “signal”. In between the minimum and maximum values are considered indeterminate.
Software defaults to LOS-Low = 1 and LOS-High = 3.
5.2.6 Polarity Invert
Polarity invert is used to swap the P and N receiver pins, which provide flexible PCB routing by
interchanging the devices physical pin to the logical signal. If the polarity of differential traces is swapped
on the PCB, the differential data can be swapped to correct it. In PIPE mode, there is an input port for
rxpolarity inversion, but that is not the case for the other modes. Polarity inversion is controlled by a
system register (INV_RX_POLARITY_LN#), not an input port for PMA/8b10b/64b6xb modes.
5.3 IO Editor for Signal Integrity
Using the Libero SoC IO Editor, the default signal Integrity parameter settings can be adjusted. These
settings are exported from the IO Editor in the PDC format along with port name, pin, direction and so on.
The io.pdc file created contains physical placement and signal integrity options of all XCVR lane
instances used in the SmartDesign.
Table 36 • LOS Range
Setting Range
PCIE Preset PCIe low threshold setting = 1
For Min and MAX values of VDETLOW, see DS0141: PolarFire FPGA Datasheet.
Preset PCIe high threshold setting = 2 For Min and MAX values of VDETLOW, see
DS0141: PolarFire FPGA Datasheet.
SATA Preset SATA low threshold setting = 2 For Min and MAX values of VDETLOW, see
DS0141: PolarFire FPGA Datasheet.
Preset SATA high threshold setting = 3 For Min and MAX values of VDETLOW, see
DS0141: PolarFire FPGA Datasheet.
0 For Min and MAX values of VDETLOW, see DS0141: PolarFire FPGA Datasheet.
1 For Min and MAX values of VDETLOW, see DS0141: PolarFire FPGA Datasheet.
2 For Min and MAX values of VDETLOW, see DS0141: PolarFire FPGA Datasheet.
3 For Min and MAX values of VDETLOW, see DS0141: PolarFire FPGA Datasheet.
4 For Min and MAX values of VDETLOW, see DS0141: PolarFire FPGA Datasheet.
5 For Min and MAX values of VDETLOW, see DS0141: PolarFire FPGA Datasheet.
6 For Min and MAX values of VDETLOW, see DS0141: PolarFire FPGA Datasheet.
7 For Min and MAX values of VDETLOW, see DS0141: PolarFire FPGA Datasheet.