Functional Description
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 47
LANE#_TX_ELEC_IDLE Input Asynchronous Transceiver configurator allows pin to be exposed
on component. This input forces XCVR_P/N
transmit output pad pair to a common-mode voltage.
This can be used for low-frequency out-of-band
signaling, or to signal entry into a low-power state to
the link partner.
LANE#_TX_BYPASS_DATA Input Asynchronous Transceiver configurator allows pin to be exposed
on component.
When LANE#_TX_BYPASS_DATA=1, the data can
be driven into the transmit pads instead of the
normal serializer data. The bypass is asynchronous
and this signal does not transit through the FWF.
This pin should be tied low if exposed to fabric and
not used.
LANE#_RX_SLIP Input RX_CLK_[R:G] LANE#_RX_SLIP assertion resets the Rx_FWF
causing LANE#_RX_VAL to momentarily
deassert(=0). Rising-edge requests that the
transceiver lane CDR slip the parallel boundary by
one bit. The direction of slip is different for 8b
parallel word modes than it is for 10b parallel word
modes. See Bit Slip, page 11.
LANE#_PCS_ARST_N
2
Input Asynchronous active-low reset for the PCS lane.
LANE#_PMA_ARST_N
2
Input Asynchronous active-low reset for the PMA lane.
LANE#_RXD_N
2
Input Transceiver receiver differential input.
LANE#_RXD_P
2
Input Transceiver receiver differential input.
LANE#_RX_DATA[N:0]
1
Output RX_CLK_[R:G] Receives data. The PF_XCVR send/receive order is
low to high byte. The first serial bit appears in bus
bit0.
LANE#_TX_CLK_STABLE
2
Output Transmits transceiver/PCS lane ready flag. This flag
is 1 when the transmit PLL is locked to the reference
clock.
LANE#_RX_VAL
2
Output LANE#_RX_VAL indicates that the XCVR data path
is initialized. The parallel bus of
LANE#_RX_DATA[N:0] contains actual data
recovered from the serial stream when
LANE#_RX_VAL = 1.
LANE#_RX_VAL is qualified when the XCVR
receiver calibration completes, included with the
enhanced receiver management completion, and
the CDR locks.
LANE#_RX_VAL pulsing low while RX_READY = 1
does not indicate that the clocking is unstable. It
means that the LANE#_RX_DATA output is all-
zeros temporarily because the Rx datapath is in
reset. If that condition does not need to be detected
for a specific application, then LANE#_ RX_VAL can
be ignored.
Lane#_RX_VAL = 1, indicates the PCS is out of
reset, which implies LANE#_RX_READY = 1
because PCS Rx is normally being held in reset
while LANE#_RX_READY = 0
Table 13 • PMA Port List (continued)
Port Name Direction Clock Description
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