Functional Description
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 24
3.3.1.1 Word Alignment (Byte Boundary or Comma Detect)
The 8b10b PCS block performs the comma code-word detection and alignment operation. The comma
character is used by the receive logic to align the incoming data stream into 10-bit words. The alignment
comma descriptions (K28.1, K28.5, and K28.7) are defined in section 36.2.4.9 of the IEEE 802.3.2002.
A comma is identified when there is a match across any 8 consecutive bits to {00111110} or {11000001}
patterns. The only legal 10b characters, which contain series of bits are K28.1, K28.5, and K28.7. In
802.3 specification definition, there is no occurrence of two legal 10b characters sent in a sequence
containing the comma pattern, which drastically reduces the chance that a symbol aligner can falsely
lock. Alignment status per lane is indicated by the LANE#_RX_VAL output pin going to high only after the
PMA CDR locks onto an incoming data stream.
Word Aligner can lock onto an incorrect alignment causing disparity errors and/or code violations from
the 8b10b decoder. In this case, the word aligner needs to be reset to find a new alignment. This can be
done by using the PCS_ARST_N reset. The fabric logic needs to monitor the
LANE#_RX_CODE_VIOLATION and LANE#_RX_DISPERROR to determine when to issue a
PCS_ARST_N and find a new alignment.
Note: Every serial protocol has a specification on how to use disparity errors and code violations to reset the
word aligner. In the XCVR 8b10b mode without a soft IP, the user must implement some type of
monitoring scheme to identify false alignments.
3.3.1.2 8b10b Data Path Interface
An 8b10b lane data path has the following interfaces:
• Fabric interface – a data path interface with soft-logic
• Internal clocks and resets interface
• PMA interface
• Parallel transmit data to the serializer
• Parallel receive data from the de-serializer
• Tx and Rx Fly-wheel FIFO (FWF)
• System registers interface – controlling modes and options
The following figure shows an overview of the 8b10b data path within the 8b10b lane. The figure does not
show specific 8b10b functional blocks (that is, encoder, aligner, decoder, and so on). The diagram is
intended to show the relative data and clock paths from the serial to fabric interface and vice-versa.
The fabric TX_DATA and RX_DATA ports are allocated to pin functions as described in the Table 7,
page 27. In addition to the fabric data pins, there are additional signals described in 8b10b port list
(Table 7, page 27). on the fabric interface for 8B10B mode.
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