Microchip Technology Microsemi UG0677 - Page 86

Functional Description
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 79
pcslane LCLK_R0 LCLK_PCS_RX
_CLK_SEL [1:0]
Defines clock
module’s source for
pcs_rx_clk.
Must be set to 2’d3 for
all applications using
8B10B function.
2’d3
LCLK_PCS_TX
_CLK_SEL [1:0]
Defines clock
module’s source for
pcs_rx_clk.
LCLK_RXFWF_
WCLK_SEL
[1:0]
Defines clock
module’s source for
rxfwf_wclk.
Must be consistent
with L8_GEARMODE
setting.
2’d2
LCLK_TXFWF_
RCLK_SEL
[1:0]
Defines clock
module’s source for
txfwf_rclk.
2’d2
LCLK_RXFWF_
WCLK_PIPE
Defines whether Rx
FWF is clocked by Tx
side clocks or Rx side
clocks.
Must be set to 1’d0 for
8B10B functionality.
1’d0
pcslane
(continued)
LCLK_R1 LCLK_ENA_8B
10B_RX_CLK
Instructs clock module
to drive 8B10B
pcs_rx_clk.
Must be set to 1’d1 for
8B10B operation.
1’d0
LCLK_ENA_8B
10B_RXFWF_
WCLK
Instructs clock module
to drive 8B10B
rxfwf_wclk.
LCLK_ENA_8B
10B_TX_CLK
Instructs clock module
to drive 8B10B
pcs_tx_clk.
LCLK_ENA_8B
10B_TXFWF_
WCLK
Instructs clock module
to drive 8B10B
txfwf_rclk.
LCLK_ENA_64
B6XB_RX_CLK
Instructs clock module
to drive 64B6xB
pcs_rx_clk.
1’d0 1’d1
LCLK_ENA_64
B6XB_RX_CLK
_DIV2
Instructs clock module
to drive 64B6xB
pcs_rx_clk_div2.
1’d0 1’d1 for 64-bit fabric
1’d0 for 32-bit fabric
LCLK_ENA_64
B6XB_TX_CLK
Instructs clock module
to drive 64B6xB
pcs_tx_clk.
1’d0 1’d1
LCLK_ENA_64
B6XB_TX_CLK
_DIV2
Instructs clock module
to drive 64B6xB
pcs_tx_clk_div2.
1’b0 1’b1 for 64-bit fabric
1’b0 for 32-bit fabric
Table 24 • System Registers Affecting 8B10B and 64B6xB Data Paths (continued)
Register
Page xls Register Name Field Name Description
Required Value for
8B10B
Required Value for
64B6xB