Functional Description
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 77
Note: Port names in Libero has prefix lane#_ appended to name
Refer to specific PCS port list tables for port description
Ports prefixed by RESERVED for a specific mode is not used for the MODE
* Port is included in CLKS_FROM_TXPLL BIF
** Port is included with Enhanced Receiver Management (ERM)
*** TX_WCLK is included when Global (Shared) TX Clock is used
The user control logic must accommodate switching transceiver control registers listed in the following
table. This is typically by modifying the registers using the DRI to the transceiver from an APB within the
design.
Output RX_DATA[63:51] RX_DATA[63:51]
Output RX_DATA[50:49] RX_DATA[50:49]
Output RX_DATA[48:9] RX_DATA[48:9]
Output RX_DATA[8:5] RX_DATA[8:5]
Output RX_DATA[4] RX_DATA[4]
Output RX_DATA[3:1] RX_DATA[3:1]
Output RX_DATA[0] RX_DATA[0]
Input TX_BIT_CLK*
Input TX_PLL_LOCK*
Input TX_PLL_REF_CLK*
Input CTRL_CLK**
Input CTRL_ARST_N**
Input CALIB_REQ**
Input LOS**
Input CDR_REF_CLK
Output CALIBRATING
Input TX_WCLK***
Input PCS_ARST_N
Input PMA_ARST_N
Output RX_VAL
Output RX_READY
Output RX_IDLE
Output TX_CLK_STABLE
Output RX_CLK_[R:G]
Output TX_CLK_[R:G]
Input RXD_P
Input RXD_N
Output TXD_P
Output TXD_N
Table 23 • Port Crossover between the 8b10b and 64b66b Modes
DIRECTION 8B10B MODE 64B6xB MODE
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