Functional Description
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 29
LANE#_RX_READY Output Asynchronous Rises when the enhanced receiver management and
CDR completes a fine lock detection to the incoming
data transitions and the de-serializer is powered-up. If
there is no incoming data to the CDR then the
RX_READY is low. The primary purpose of this pin is to
let the fabric know the CDR is locked to serial input data
and is producing valid clocking.
Note: In a loopback case where looping the local
transmitter output to the receiver input, it is necessary to
take the Tx out of reset to ensure valid serial transitions,
allowing the Rx CDR to lock. If the user waits till Rx
CDR locks before releasing Tx from reset, in such a
case, the system deadlocks.
LANE#_RX_IDLE Output Asynchronous Receive Electrical Idle (EI) detection flag. Flag is 1
when EI is valid. LANE#_Rx_IDLE peak detector logic
is only valid for a limited minimum density of transitions
on the Rx data and not to be used in applications above
5Gbps.
LANE#_TX_CLK_STABLE Output Transmit transceiver/PCS lane ready flag. This flag is 1
when the transmit PLL is locked to the reference clock.
LANE#_RX_CLK_[R:G] Output Global or regional receive clock to the fabric.
4
LANE#_TX_CLK_[R:G]
5
Output Global or regional transmit clock to the fabric.
4
LANE#_TXD_N Output Transceiver transmitter differential output.
LANE#_TXD_P Output Transceiver transmitter differential output.
1. N can be 1, 3, 7, and 15.
2. N can be 1, 3, and 7.
3. N can be 15, 31, and 63.
4. [R:G] naming is generated based on the use of regional or global resources that are selected with Libero.
Note: LANE# can be 0, 1, 2, and 3.
5. In MPF500 devices, the TX_CLK_R and RX_CLK_R pins of XCVR lanes placed in the PCIESS (Q0) and GPSS1 (Q1) quads
cannot drive I/Os.
Table 7 • 8b10b Port List (continued)
Port Name Direction Clock Description
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