Functional Description
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 28
LANE#_TX_DATA[N:0] Input TX_CLK_[R:G] Encoded user data from the fabric. The send/receive
order is low to high byte.
LANE#_PCS_ARST_N Input Asynchronous active-low reset for the PCS lane. This
reset is responsible for the reset of the 8b10b logic and
COMMA word aligner. The RX_SLIP is internally used
to align the parallel word on the fabric interface, but
does not reset the word aligner.
LANE#_PMA_ARST_N Input Asynchronous active-low reset for the PMA lane.
LANE#_RXD_N Input Transceiver receiver differential input.
LANE#_RXD_P Input Transceiver receiver differential input.
LANE#_8B10B_RX_K[N:0]
2
Output RX_CLK_[R:G] Active-high output from the decoder to the receiver
indicating that the received data is a K character. The
order of character bits within an octet, in 8b10b mode, is
least to most-significant bit as defined by 8b10b code
notation.
[0]: K decoded data on RX_DATA[7:0].
[1]: K decoded data on RX_DATA[15:8].
LANE#_RX_DISPARITY_
ERROR[N:0]
2
Output RX_CLK_[R:G] Active-high output indicates when the received code
group exists in the 8b10b decoding table but is not
found in the proper column according to the current
running disparity.
LANE#_RX_CODE_
VIOLATION[N:0]
2
Output RX_CLK_[R:G] Active-high signal indicating that the decoder has
detected an error in the received data.
LANE#_RX_DATA[N:0]
3
Output RX_CLK_[R:G] Decoded user data to fabric. The send/receive data
order is low to high byte meaning the octet order is least
to most-significant.
Data[7:0] = First octet
Data[15:8] = Second octet
LANE#_RX_VAL Output Asynchronous LANE#_RX_VAL indicates that the XCVR data path is
initialized. The parallel bus of LANE#_RX_DATA[N:0]
contains actual data recovered from the serial stream
when LANE#_RX_VAL = 1.
In 8b10b mode, the Rx PCS logic self-resets when the
CDR is not locked. In this mode, LANE#_RX_VAL rises
just after LANE#_RX_READY rises. Always pulse
LANE#_PCS_ARST_N=0 using a clock independent
from the LANE#_RX_CLK_R transceiver output.
Asserting and holding LANE#_PCS_ARST_N=0 can
prevent LANE#_PCS_RX_READY from rising and hold
LANE#_RX_CLK_R at a static level.
In 8b10b mode, the LANE#_RX_VAL is qualified when
XCVR receiver calibration completes, included with the
enhanced receiver management completion, and the
CDR locks and the initial comma/word alignment
occurs.
Table 7 • 8b10b Port List (continued)
Port Name Direction Clock Description
To Next Page
Loading...