Board Design Recommendations
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 126
XCVR_#_RX2_N Input Receive data. Transceiver differential negative input. Each
transceiver quad consists of four receive– signals.
XCVR_#_RX1_N Input Receive data. Transceiver differential negative input. Each
transceiver quad consists of four receive– signals.
XCVR_#_RX0_N Input Receive data. Transceiver differential negative input. Each
transceiver quad consists of four receive– signals.
XCVR_#[A,B,C]_REFCLK_P
3
Input This pin is used as the positive terminal when used with a differential
clock source.
XCVR_#[A,B,C]_REFCLK_N
3
Input This pin is used as the negative terminal when used with a differential
clock.
XCVR_VREF Power This pin is used as a reference voltage for the REFCLK input buffers.
It is used for single-ended clock signals. This signal is common for all
transceiver on device.
VDDA25 Power 2.5 V analog supply. All transmit PLLs and associated high-speed
clock routes in each transceiver PMA are connected on-chip but
isolated from the other transmit PLLs on the device.
VDDA Power Supply for receive, transmit, and common circuits. Common for all
lanes within the PMA block.
VDD_XCVR_CLK Power Provides common power to all transceiver reference clock buffers.
VDD_XCVR_CLK power supply operates using a voltage of
2.5 V to 3.3 V.
1. See the related PolarFire Package Pin Assignment Table for recommended USED or UNUSED conditions.
2. # Indicates the associated transceiver quad (that is, Q0=0, Q1=1, …Q5=5).
3. There is one pin per transmit PLL per transceiver quad. There is a minimum of two differential reference clock input pairs per quad
with an additional pair for specific quads. It is limited to driving only one clock source for the transceiver block when used
differentially or two when used in the single-ended mode.
Table 39 • Transceiver Device Level Pin List (continued)
1
Pin Name
2
Direction Description
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