Functional Description
Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0 74
The functionality of the resets are register configured by the Libero software. See the PolarFire Device
Register Map for information about register maps. After Libero programming, these register controlled
bits are written at power up prior to releasing the Tx PLL from reset. By doing this configuration during
reset guarantees that the PCS Tx is reset without manual intervention.
In PMA Only XCVR configurations, the PCS_ARST_N can be tied to 1. This configuration assumes that
the PCSLANE/LRST_R0/LRST_ULCKD_CDR_RESETS_PCS_RX register is set to 0x1 (default). This
configuration resets the fly-wheel FIFOs within the PCS for PMA Only modes when the CDR
automatically resets PCS Rx domain logic.
Libero PCS_ARST_N settings: only reset the Rx PCS when PCS_ARST_N falls; and self-reset the Tx
PCS when the Tx PLL transitions from unlocked to locked. The Tx PLL lock is typically the last event
which impacts the health of the clock going into the PCS from the PMA. However, if there is an
application which requires a change to serializer post-divider or change to which PLL a particular Tx lane
uses; these events cause a change in PCS clocking. These types of configuration changes should be
carried out by first asserting the soft PCS Tx Reset system register, then changing the serializer
configuration, and then de-asserting the soft PCS Tx Reset system register. This method assures the
PCS plus its FWF sees a consistent clocking at the time when they are out of reset. Rate modifications
must be done through DRI using a reset/modify/unreset sequence and must be implemented by the user
design. For such rate changes, the *ARST_N pins do not have to be used since soft resets are available
through the DRI.
In 8b10b mode, the word aligner can only find a new pattern following a reset. Therefore, the Libero
default is for PCS_ARST_N for Rx Only.
See Transceiver Modes, page 99 for information about the impact of PMA and PCS resets.
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