R&S ZVB - Page 615

R&S
®
ZVA / R&S
®
ZVB / R&S
®
ZVT Remote Control
Status Reporting System
Operating Manual 1145.1084.12 – 30 600
Bit
No.
Meaning
0
Operation Complete
This bit is set on receipt of the command *OPC after all previous commands have been executed.
2
Query Error
This bit is set if either the controller wants to read data from the instrument without having sent a query, or if it does not
fetch requested data and sends new instructions to the instrument instead. The cause is often a query which is faulty and
hence cannot be executed.
3
Device-Dependent Error
This bit is set if a device-dependent error occurs. An error message with a number between -300 and -399 or a positive
error number, which describes the error in greater detail, is entered into the error queue (see chapter Error Messages).
4
Execution Error
This bit is set if a received command is syntactically correct, but cannot be performed for other reasons. An error message
with a number between -200 and -300, which describes the error in greater detail, is entered into the error queue (see
chapter Error Messages).
5
Command Error
This bit is set if a command which is undefined or syntactically incorrect is received. An error message with a number
between -100 and -200, which describes the error in greater detail, is entered into the error queue (see chapter Error
Messages).
6
User Request
This bit is set when the instrument is switched over to manual control or when a user-defined softkey is used
(SYSTem:USER:KEY...).
7
Power On (supply voltage on)
This bit is set when the instrument is switched on.
STATus:OPERation
The STATus:OPERation register contains conditions which are part of the instrument's normal operation.
The analyzer does not use the STATus:OPERation register.
STATus:QUEStionable
The STATus:QUEStionable register indicates whether the acquired data is of questionable quality and
monitors hardware failures of the analyzer. It can be queried using the commands
STATus:QUEStionable:CONDition? or STATus:QUEStionable[:EVENt]?
The bits in the STATus:QUEStionable register are defined as follows:
Bit No.
Meaning
9
INTegrity register summary
This bit is set if a bit is set in the STATus:QUEStionable:INTegrity register and the associated ENABle bit is set to 1.
10
LIMit register summary
This bit is set if a bit is set in the STATus:QUEStionable:LIMit1 register and the associated ENABle bit is set to 1.