Anritsu MT8820A - Standard Event Status Register

7.6 Status Report
7-17
7.6.2 Standard event status register
SESR: Standard Event Status Register is a register consisting of eight bits. Each bit
is respectively assigned to a standard event. When the MT8820A enters a standard
event status, the corresponding bit becomes 1 (true).
＆
＆
＆
＆
＆
＆
＆
＆
Logical OR
Power-On (PON)
User Request (URQ)
Command Error (CME)
Execution Error (EXE)
Device Dependent Error (DDE)
Query Error (QYE)
Request Control (RQC)
Operation Completed (OPC)
Standard Event Status Enable Register
Standard Event Status Register
7
6
5
4
3
2
1
0
Reads by ∗ESR?Sets by ∗ESE <n>
Reads by ∗ESE?
7
6
5
4
3
2
1
0
disabled=0, enabled=128(2
7
)
disabled=0, enabled=64 (2
6
)
disabled=0, enabled=32 (2
5
)
disabled=0, enabled=16 (2
4
)
disabled=0, enabled=8 (2
3
)
disabled=0, enabled=4 (2
2
)
disabled=0, enabled=2 (2
1
)
disabled=0, enabled=1 (2
0
)
ESB summary message bit
(To bit 5 of status byte register)
Fig. 7-6-2-1 Standard event status register