Debug Interface
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 5-3
5.1.2 Clocks
The ARM7TDMI core has two clocks:
• MCLK is the memory clock
• DCLK is an internal debug clock, generated by the test clock, TCK.
During normal operation, the core is clocked by MCLK and internal logic holds DCLK
LOW.
When the ARM7TDMI processor is in halt mode, the core is clocked by DCLK under
control of the TAP state machine and MCLK can free-run. The selected clock is output
on the signal ECLK for use by the external system.
Note
NWAIT must be HIGH in debug state.
In monitor mode, the core continues to be clocked by MCLK, and DCLK is not used.
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