ARM ARM7TDMI - Page 196

AC and DC Parameters
7-24 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
T
opcd
MCLKr to nOPC valid Maximum Figure 7-1 on page 7-3
T
opch
nOPC hold time from MCLKr Minimum Figure 7-1 on page 7-3
T
rg
MCLKf to RANGEOUT0, RANGEOUT1 valid Maximum Figure 7-13 on page 7-12
T
rgh
RANGEOUT0, RANGEOUT1 hold time from MCLKf Minimum Figure 7-13 on page 7-12
T
rm
Reset guaranteed nonrecognition time Maximum Figure 7-11 on page 7-11
T
rqh
DBGRQ guaranteed non-recognition time Minimum Figure 7-13 on page 7-12
T
rqs
DBGRQ set up time to MCLKr for guaranteed recognition Minimum Figure 7-13 on page 7-12
T
rs
Reset setup time to MCLKr for guaranteed recognition Minimum Figure 7-11 on page 7-11
T
rstd
nRESETf to D[31:0], DBGACK, nCPI, nENOUT, nEXEC,
nMREQ, SEQ valid
Maximum Figure 7-19 on page 7-17
T
rstl
nRESET LOW for guaranteed reset Minimum Figure 7-19 on page 7-17
T
rwd
MCLKr to nRW valid Maximum Figure 7-1 on page 7-3
T
rwh
nRW hold time from MCLKr Minimum Figure 7-1 on page 7-3
T
sdtd
SDOUTBS to TDO valid Maximum -
T
shbsf
TCK to SHCLKBS, SHCLK2BS falling Maximum -
T
shbsr
TCK to SHCLKBS, SHCLK2BS rising Maximum -
T
sih
Synchronous nFIQ, nIRQ hold from MCLKf with ISYNC=1 Minimum Figure 7-12 on page 7-12
T
sis
Synchronous nFIQ, nIRQ setup to MCLKf, with ISYNC=1 Minimum Figure 7-12 on page 7-12
T
tbe
Address and Data bus enable time from TBEr Maximum Figure 7-6 on page 7-8
T
tbz
Address and Data bus disable time from TBEf Maximum Figure 7-6 on page 7-8
T
tckf
TCK to TCK1, TCK2 falling Maximum -
T
tckr
TCK to TCK1, TCK2 rising Maximum -
T
tdbgd
TCK to DBGACK, DBGRQI changing Maximum -
T
tpfd
TCKf to TAP outputs Maximum -
Table 7-23 AC timing parameters used in this chapter (continued)
Symbol Parameter
Parameter
type
Figure cross
reference